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riscv-gcc-1
Commit 113c53c3 by Wilco Dijkstra Committed by Wilco Dijkstra
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[Arm] Cleanup IT attributes 

A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in
ITs block even when arm_restrict_it was enabled.  Rather than just fixing this
latent issue, change the default of predicable_short_it to "no" so that only
16-bit instructions need to be marked with it.  As a result there are far fewer
patterns that need the attribute, and omitting predicable_short_it is no longer
causing issues.

	* config/arm/arm.md (predicable_short_it): Change default to "no",
	improve documentation, remove uses that are identical to the default.
	(enabled_for_depr_it): Rename to enabled_for_short_it.
	* gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
	* gcc/config/arm/ldmstm.md (predicable_short_it): Likewise.
	* gcc/config/arm/sync.md (predicable_short_it): Likewise.
	* gcc/config/arm/thumb2.md (predicable_short_it): Likewise.
	* gcc/config/arm/vfp.md (predicable_short_it): Likewise.

From-SVN: r254463
parent aeed6d61
Showing with 55 additions and 96 deletions
gcc/ChangeLog
2017-11-06 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (predicable_short_it): Change default to "no",
improve documentation, remove uses that are identical to the default.
(enabled_for_depr_it): Rename to enabled_for_short_it.
* gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
* gcc/config/arm/ldmstm.md (predicable_short_it): Likewise.
* gcc/config/arm/sync.md (predicable_short_it): Likewise.
* gcc/config/arm/thumb2.md (predicable_short_it): Likewise.
* gcc/config/arm/vfp.md (predicable_short_it): Likewise.
2017-11-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/82748
gcc/config/arm/arm-fixed.md
......@@ -35,7 +35,6 @@
"TARGET_INT_SIMD"
"sadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "usadd<mode>3"
......@@ -45,7 +44,6 @@
"TARGET_INT_SIMD"
"uqadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "ssadd<mode>3"
......@@ -55,7 +53,6 @@
"TARGET_INT_SIMD"
"qadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "sub<mode>3"
......@@ -75,7 +72,6 @@
"TARGET_INT_SIMD"
"ssub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "ussub<mode>3"
......@@ -86,7 +82,6 @@
"TARGET_INT_SIMD"
"uqsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "sssub<mode>3"
......@@ -96,7 +91,6 @@
"TARGET_INT_SIMD"
"qsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
;; Fractional multiplies.
......@@ -414,7 +408,6 @@
"TARGET_32BIT && arm_arch6"
"ssat%?\\t%0, #16, %2%S1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
(set_attr "type" "alu_shift_imm")])
......@@ -424,6 +417,5 @@
"TARGET_INT_SIMD"
"usat%?\\t%0, #16, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_imm")]
)
gcc/config/arm/ldmstm.md
......@@ -37,8 +37,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation"
......@@ -75,8 +74,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmia%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm4_ia_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -110,8 +108,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -128,8 +125,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmia%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -306,8 +302,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*ldm4_db_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -328,8 +323,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmdb%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm4_db"
[(match_parallel 0 "store_multiple_operation"
......@@ -344,8 +338,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm4_db_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -362,8 +355,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmdb%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
......@@ -485,8 +477,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%?\t%4, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation"
......@@ -517,8 +508,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmia%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm3_ia_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -547,8 +537,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%?\t%4, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -563,8 +552,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmia%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -716,8 +704,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%4, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*ldm3_db_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -735,8 +722,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm3_db"
[(match_parallel 0 "store_multiple_operation"
......@@ -749,8 +735,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%4, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm3_db_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -765,8 +750,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
......@@ -871,8 +855,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldm%?\t%3, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation"
......@@ -897,8 +880,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmia%?\t%3!, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm2_ia_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -922,8 +904,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%?\t%3, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm2_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -936,8 +917,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmia%?\t%3!, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_stm2_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -1064,8 +1044,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldmdb%?\t%3, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*ldm2_db_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -1080,8 +1059,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%3!, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm2_db"
[(match_parallel 0 "store_multiple_operation"
......@@ -1092,8 +1070,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stmdb%?\t%3, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm2_db_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -1106,8 +1083,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%3!, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
......
gcc/config/arm/sync.md
......@@ -87,8 +87,7 @@
}
}
[(set_attr "arch" "32,v8mb,any")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "atomic_store<mode>"
[(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q")
......@@ -115,8 +114,7 @@
}
}
[(set_attr "arch" "32,v8mb,any")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets
......@@ -127,8 +125,7 @@
VUNSPEC_LDRD_ATOMIC))]
"ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"
"ldrd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
;; There are three ways to expand this depending on the architecture
;; features available. As for the barriers, a load needs a barrier
......@@ -461,8 +458,7 @@
ldrex<sync_sfx>%?\t%0, %C1
ldrex<sync_sfx>\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
......@@ -475,8 +471,7 @@
ldaex<sync_sfx>%?\\t%0, %C1
ldaex<sync_sfx>\\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
......@@ -488,8 +483,7 @@
ldrex%?\t%0, %C1
ldrex\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
......@@ -501,8 +495,7 @@
ldaex%?\t%0, %C1
ldaex\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
......@@ -511,8 +504,7 @@
VUNSPEC_LL))]
"TARGET_HAVE_LDREXD"
"ldrexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
......@@ -521,8 +513,7 @@
VUNSPEC_LAX))]
"TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
"ldaexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_store_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
......@@ -548,8 +539,7 @@
else
return "strex<sync_sfx>%?\t%0, %2, %C1";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_store_release_exclusivedi"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
......@@ -564,8 +554,7 @@
gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
return "stlexd%?\t%0, %2, %H2, %C1";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_store_release_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
......@@ -579,5 +568,4 @@
stlex<sync_sfx>%?\t%0, %2, %C1
stlex<sync_sfx>\t%0, %2, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
gcc/config/arm/thumb2.md
......@@ -34,7 +34,6 @@
"TARGET_THUMB2"
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "alu_shift_imm")]
)
......@@ -57,7 +56,7 @@
(match_dup 2)))]
""
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "length" "6,6,10")
(set_attr "type" "multiple")]
)
......@@ -78,7 +77,7 @@
(match_dup 2)))]
""
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "length" "6,6,10")
(set_attr "type" "multiple")]
)
......@@ -100,7 +99,7 @@
""
[(set_attr "conds" "clob")
(set_attr "length" "6,6,10")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "type" "multiple")]
)
......@@ -121,7 +120,7 @@
""
[(set_attr "conds" "clob")
(set_attr "length" "6,6,10")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "type" "multiple")]
)
......@@ -172,8 +171,7 @@
[(set_attr "conds" "*,clob,clob")
(set_attr "shift" "1")
(set_attr "predicable" "yes,no,no")
(set_attr "predicable_short_it" "no")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "ce_count" "2")
(set_attr "length" "8,6,10")
(set_attr "type" "multiple")]
......@@ -226,8 +224,7 @@
[(set_attr "conds" "*,clob,clob")
(set_attr "shift" "1")
(set_attr "predicable" "yes,no,no")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "predicable_short_it" "no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "ce_count" "2")
(set_attr "length" "8,6,10")
(set_attr "type" "multiple")]
......@@ -354,7 +351,7 @@
(const_int 0)))]
""
[(set_attr "conds" "use")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "8,10")
(set_attr "type" "multiple")]
)
......@@ -504,7 +501,7 @@
DONE;
}
[(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
(set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
(set_attr "enabled_for_short_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
(set_attr "conds" "use")
(set_attr_alternative "type"
[(if_then_else (match_operand 2 "const_int_operand" "")
......@@ -1044,7 +1041,6 @@
ldrsb%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
......@@ -1058,7 +1054,6 @@
ldrh%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
......@@ -1072,7 +1067,6 @@
ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
......@@ -1538,7 +1532,6 @@
"TARGET_THUMB2"
"orn%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
......@@ -1551,7 +1544,6 @@
"TARGET_THUMB2"
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "alu_shift_imm")]
)
......
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