In cases that we need to extended the lifetime of a temporary captured
by reference, we make a replacement var for the temporary.  This will
be then used to define a coroutine frame entry (so that the var created
is elided by a later phase).  However, we should ensure that the var
is correctly declared anyway.

gcc/cp/ChangeLog:

2020-04-07  Iain Sandoe  <iain@sandoe.co.uk>

	* coroutines.cc (maybe_promote_captured_temps): Ensure that
	reference capture placeholder vars are properly declared.

This patch adds C++ polymorphism for the MVE intrinsics, by using the native C++
polymorphic functions when C++ is used.

It also moves the PRESERVE name macro definitions to the right place so that the
variants without the '__arm_' prefix are not available if we define the PRESERVE
NAMESPACE macro.

This patch further fixes two testisms that were brought to light by C++ testing
added in this patch.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* g++.target/arm/mve.exp: New.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16: Fix testism.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32: Likewise.

This patch fixes the passing of some pointers to builtins that expect slightly
different types of pointers.  In C this didn't prove an issue, but when
compiling for C++ gcc complains.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h: Cast some pointers to expected types.

This patch fixes some testisms I found when testing using -Wall/-Werror.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Fix testism.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise.

This patch replaces all uses of 'vuninitializedq_*' by the same function but
under the __arm_ namespace. In case we define the PRESERVE MACRO the variant
without the '__arm_' prefix will not be available.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
	same with '__arm_' prefix.

This patch fixes vec extracts to memory that can arise from code as seen in the
testcase added. The patch fixes this by allowing mem operands in the set of
mve_vec_extract patterns, which given the only '=r' constraint will lead to the
scalar value being written to a register and then stored in memory using scalar
store pattern.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c: New
	test.

Hi,

This patch fixes the immediate checks on vcvt and vqshr(u)n[bt] instructions.
It also removes the 'arm_mve_immediate_check' as the check was wrong and the
error message is not much better than the constraint one, which albeit isn't
great either.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.c (arm_mve_immediate_check): Removed.
	* config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
	(mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
	 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
	 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
	 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
	 mve_vqshruntq_m_n_s*): Fixed immediate constraints.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c: New test.

After fixing the v[id]wdups using the "moving the wrap parameter" into the
top-end of a DImode operand using a shift, I noticed we were using lsll for
32-bit shifts in scalars, where we don't need to, as we can simply do a move,
  which is much better if we don't need to use the bottom part.

We can solve this in a better way, but for now this will do.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.

This patch fixes v[id]wdup intrinsics. They had two issues:
1) the predicated versions did not link the incoming inactive vector parameter
to the output
2) The backend didn't enforce the wrap limit operand be in an odd register.

1) was fixed like we did for all other predicated intrinsics
2) requires a temporary hack where we pass the value in the top end of DImode
operand. The proper fix would be to add a register CLASS but this interacted
badly with other existing targets codegen.  We will look to fix this properly in GCC 11.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
	* config/arm/mve/md: Fix v[id]wdup patterns.

This patch fixes the constant load pattern for MVE, this was not accounting
correctly for label + offset cases.

Added test that ICE'd before and removed the scan assemblers for the mve_vector*
tests as they were too fragile.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.c (output_move_neon): Deal with label + offset cases.
	* config/arm/mve.md (*mve_mov<mode>): Handle const vectors.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_load_from_array.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_vector_float.c: Remove
	scan-assembler.
	* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.

To make sure our inlining of _Generic doesn't go crazy we added an in between
declaration of the parameters used for _Generic selection. However, this will
not work if the parameter being passed in is an array.  Since none of our
intrinsics return pointers we do not need to use typeof here as we will never be
able to nest intrinsics through this parameter. I also removed the unnecessary
const pointers in mve_typeid.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
	and remove const_ptr enums.

This patch merges some polymorphic functions that were uncorrectly separating
scalar variants. It also simplifies the way we detect scalars and constants in
mve_typeid.

I also fixed some polymorphic intrinsics that were splitting of scalar cases.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h (vsubq_n): Merge with...
	(vsubq): ... this.
	(vmulq_n): Merge with...
	(vmulq): ... this.
	(__ARM_mve_typeid): Simplify scalar and constant detection.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Fix test.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.

The ordering of some fields in  struct sigaction on s390x (64bit)
differs compared to s390 and other architectures.
This patch adjusts this order according to the definition of
<glibc-src>/sysdeps/unix/sysv/linux/s390/bits/sigaction.h

Without this fix e.g. the call
sigaction( suspendSignalNumber, &sigusr1, null ) in thread.d
leads to setting the sa_restorer field to 0xffffffffffffffff.
In case a signal, the signal handler returns to this address
and the process stops with a SIGILL.

This was observable in several execution testcases on s390x:
libphobos.druntime/core/thread.d
libphobos.druntime_shared/core/thread.d
libphobos.thread/tlsgc_sections.d
libphobos.allocations/tls_gc_integration.d
libphobos.phobos/std/parallelism.d
libphobos.phobos_shared/std/parallelism.d
libphobos.shared/host.c
libphobos.shared/linkD.c
libphobos.shared/linkDR.c
libphobos.shared/link_linkdep.d
libphobos.shared/load.d
libphobos.shared/loadDR.c
libphobos.shared/load_linkdep.d
libphobos.shared/load_loaddep.d

libphobos/ChangeLog:

2020-04-07  Stefan Liebler  <stli@linux.ibm.com>

	* libdruntime/core/sys/posix/signal.d:
	Add struct sigaction_t for SystemZ.

This PR reports that ever since the introduction of the
CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag, we are sometimes failing to resolve
PLACEHOLDER_EXPRs inside array initializers that refer to some inner
constructor.  In the testcase in the PR, we have as the initializer for "S c[];"
the following

  {{.a=(int &) &_ZGR1c_, .b={*(&<PLACEHOLDER_EXPR struct S>)->a}}}

where CONSTRUCTOR_PLACEHOLDER_BOUNDARY is set on the middle constructor.  When
calling replace_placeholders from store_init_value, we pass the entire
initializer to it, and as a result we fail to resolve the PLACEHOLDER_EXPR
within due to the CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag on the middle
constructor blocking replace_placeholders_r from reaching it.

To fix this, we could perhaps either call replace_placeholders in more places,
or we could change where we set CONSTRUCTOR_PLACEHOLDER_BOUNDARY.  This patch
takes this latter approach -- when building up an array initializer, we now
bubble any CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag from the element initializers
up to the array initializer so that the boundary doesn't later impede us when we
call replace_placeholders from store_init_value.

Besides fixing the kind of code like in the testcase, this shouldn't cause any
other differences in PLACEHOLDER_EXPR resolution because we don't create or use
PLACEHOLDER_EXPRs of array type in the frontend, as far as I can tell.

gcc/cp/ChangeLog:

	PR c++/90996
	* tree.c (replace_placeholders): Look through all handled components,
	not just COMPONENT_REFs.
	* typeck2.c (process_init_constructor_array): Propagate
	CONSTRUCTOR_PLACEHOLDER_BOUNDARY up from each element initializer to
	the array initializer.

gcc/testsuite/ChangeLog:

	PR c++/90996
	* g++.dg/cpp1y/pr90996.C: New test.

The following testcases are miscompiled, because expand_vec_perm_pshufb
incorrectly thinks it can use vpshufb instruction for the permutations
when it can't.
The
          if (vmode == V32QImode)
            {
              /* vpshufb only works intra lanes, it is not
                 possible to shuffle bytes in between the lanes.  */
              for (i = 0; i < nelt; ++i)
                if ((d->perm[i] ^ i) & (nelt / 2))
                  return false;
            }
intra-lane check which is correct has been copied and adjusted for 64-byte
modes into:
          if (vmode == V64QImode)
            {
              /* vpshufb only works intra lanes, it is not
                 possible to shuffle bytes in between the lanes.  */
              for (i = 0; i < nelt; ++i)
                if ((d->perm[i] ^ i) & (nelt / 4))
                  return false;
            }
which is not correct, because 64-byte modes have 4 lanes rather than just
two and the above is only testing that the permutation grabs even lane elts
from even lanes and odd lane elts from odd lanes, but not that they are
from the same 256-bit half.

The following patch fixes it by using 3 * nelt / 4 instead of nelt / 4,
so we actually check the most significant 2 bits rather than just one.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR target/94509
	* config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
	for inter-lane permutation for 64-byte modes.

	* gcc.target/i386/avx512bw-pr94509-1.c: New test.
	* gcc.target/i386/avx512bw-pr94509-2.c: New test.

We need to set OMP_PARALLEL_COMBINED only if the parsing of omp_master
succeeded, because otherwise there is no nested master construct in the
parallel.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR c++/94512
	* c-parser.c (c_parser_omp_parallel): Set OMP_PARALLEL_COMBINED
	if c_parser_omp_master succeeded.

	* parser.c (cp_parser_omp_parallel): Set OMP_PARALLEL_COMBINED
	if cp_parser_omp_master succeeded.

	* g++.dg/gomp/pr94512.C: New test.

The following testcase ICEs on aarch64 apparently since the introduction of
the aarch64 port.  The reason is that the {ashl,ashr,lshr}<mode>3 expanders
completely unnecessarily FAIL; if operands[2] is something other than
a CONST_INT or REG or MEM and the middle-end code can't cope with the
pattern giving up in these cases.  All the expanders use general_operand
predicate for the shift amount operand, but then have just a special case
for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
REG), or MEM (force into REG), or REG (that is the case it handles).
In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
general_operand.
I don't see any reason what is magic about MEMs that it should be forced
into REG and others like SUBREGs that it shouldn't, there isn't even a
reason to check for !REG_P because force_reg will do nothing if the operand
is already a REG, and otherwise can handle general_operand just fine.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR target/94488
	* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
	ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
	Assume it is a REG after that instead of testing it and doing FAIL
	otherwise.  Formatting fix.

	* gcc.c-torture/compile/pr94488.c: New test.

gcc/d/ChangeLog:

	PR d/94425
	* toir.cc (IRVisitor::visit (GccAsmStatement *)): Set ASM_VOLATILE_P
	on all asm statements.

The support for the 32-bit float GPRs was removed in GCC 8.

gcc/

	* config/rs6000/t-rtems: Delete mcpu=8540 multilib.

The following testcase is miscompiled in 8.x, because emit_reduc_half is
prepared to handle for 512-bit modes only i equal to 512, 256, 128 and 64.
V32HImode also needs i equal to 32 and V64QImode i equal to 32 and 16,
but emit_reduc_half in that case performs a redundant permutation exactly
like i == 32.  In 9+ the testcase works because Richard in r9-3393
changed the reduc_* expanders so that they actually don't call
ix86_expand_reduc on 512-bit modes, but only 128-bit ones.

The patch fixes emit_reduc_half to handle also i of 32 and 16 similarly to
how V32QImode/V16HImode are handled for AVX2.  I think it shouldn't hurt
to fix the function even on the trunk and 9 branch even when nothing uses
it ATM.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR target/94500
	* config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
	handle i < 64 using avx512bw_lshrv4ti3.  Formatting fixes.

	* gcc.target/i386/avx512bw-pr94500.c: New test.

duplicate_decls assumed that any TREE_ARTIFICIAL function at namespace scope
was a built-in function, but now in C++20 it's possible to have an
implicitly declared hidden friend operator==.  We just need to move the
assert into the if condition.

gcc/cp/ChangeLog
2020-04-06  Jason Merrill  <jason@redhat.com>

	PR c++/94462
	* decl.c (duplicate_decls): Fix handling of DECL_HIDDEN_FRIEND_P.

Update to edea4a79e8d7dea2456b688f492c8af33d381dc2 which is likely to
be approximately the 1.14.2 release.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/227377

Fix a problem with commit c8e759b4 ("libgomp/test: Fix compilation
for build sysroot") that caused a regression in some standalone test
environments where testsuite/libgomp-test-support.exp is used, but the
compiler is expected to be determined by `[find_gcc]', and set the
GCC_UNDER_TEST TCL variable in testsuite/libgomp-site-extra.exp instead.

	libgomp/
	* configure.ac: Add testsuite/libgomp-site-extra.exp to output
	files.
	* configure: Regenerate.
	* testsuite/libgomp-site-extra.exp.in: New file.
	* testsuite/libgomp-test-support.exp.in (GCC_UNDER_TEST): Remove
	variable.
	* testsuite/Makefile.am (EXTRA_DEJAGNU_SITE_CONFIG): New
	variable.
	* testsuite/Makefile.in: Regenerate.

Fix a problem with the libatomic testsuite using a method to determine
the compiler to use resulting in the tool being different from one the
library has been built with, and causing a catastrophic failure from the
lack of a suitable `--sysroot=' option where the `--with-build-sysroot='
configuration option has been used to build the compiler resulting in
the inability to link executables.

Address this problem by providing a DejaGNU configuration file defining
the compiler to use, via the GCC_UNDER_TEST TCL variable, set from $CC
by autoconf, which will have all the required options set for the target
compiler to build executables in the environment configured, removing
failures like:

.../bin/riscv64-linux-gnu-ld: cannot find crt1.o: No such file or directory
.../bin/riscv64-linux-gnu-ld: cannot find -lm
collect2: error: ld returned 1 exit status
compiler exited with status 1
FAIL: libatomic.c/atomic-compare-exchange-1.c (test for excess errors)
Excess errors:
.../bin/riscv64-linux-gnu-ld: cannot find crt1.o: No such file or directory
.../bin/riscv64-linux-gnu-ld: cannot find -lm

UNRESOLVED: libatomic.c/atomic-compare-exchange-1.c compilation failed to produce executable

and bringing overall test results for the `riscv64-linux-gnu' target
(here with the `x86_64-linux-gnu' host and RISC-V QEMU in the Linux user
emulation mode as the target board) from:

		=== libatomic Summary ===

# of unexpected failures	27
# of unresolved testcases	27

to:

		=== libatomic Summary ===

# of expected passes		54

	libatomic/
	* configure.ac: Add testsuite/libatomic-site-extra.exp to output
	files.
	* configure: Regenerate.
	* libatomic/testsuite/libatomic-site-extra.exp.in: New file.
	* testsuite/Makefile.am (EXTRA_DEJAGNU_SITE_CONFIG): New
	variable.
	* testsuite/Makefile.in: Regenerate.

getopt.c hangs the compiler on h8300-elf with -O2 -g, because the
IL contains addition of constant 0, the first PLUS operand is determined
to have the SP_DERIVED_VALUE_P and the new code in cselib recurses
indefinitely on seeing SP_DERIVED_VALUE_P with locs of
(plus:P SP_DERIVED_VALUE_P (const_int 0)).

Fixed by making sure cselib_subst_to_values canonicalizes it, hashing
already hashes it the same too.

2020-04-06  Jakub Jelinek  <jakub@redhat.com>

	* cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
	+ const0_rtx return the SP_DERIVED_VALUE_P.

	* sv.po: Update.

	* eo.po: Update.

gcc/fortran/ChangeLog:

2020-04-06  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/93686
	* decl.c (gfc_match_data): Handle data matching for derived type
	pointers.

gcc/testsuite/ChangeLog:

2020-04-06  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/93686
	* gfortran.dg/pr93686_1.f90: New test.
	* gfortran.dg/pr93686_2.f90: Likewise.
	* gfortran.dg/pr93686_3.f90: Likewise.
	* gfortran.dg/pr93686_4.f90: Likewise.

This test verifies, by using a weak reference to _Unwind_RaiseException,
that performing division by zero does not cause that symbol to get
indirectly pulled into our closure.

The testing methodology unfortunately does not work on VxWorks targets
when building in kernel mode. This is inherent to how kernel mode
on VxWorks works: The link is only partial and the remaining symbols
which have not been resolved already get automatically resolved by
the VxWorks loader at the moment the module is loaded onto the target,
prior to execution. The resolution includes weak symbols too, which
defeats the purpose of this test.

gcc/testsuite/

        * gcc.target/arm/div64-unwinding.c: Skip on vxworks_kernel targets.

lra_assign has an assert to make sure that no pseudo is allocated
to a conflicting hard register.  It used to be restricted to
!flag_ipa_ra, but in g:a1e6ee38 I'd enabled it for
flag_ipa_ra too.  It then tripped a few times while building
libstdc++ for mips-mti-linux.

Previous patches fixed one of the problems: registers clobbered
by the taking of an exception were being treated as live at the
beginning of the EH receiver, and this got propagated to predecessor
blocks.  But it turns out that there was a second problem: eh_return
data registers were also being marked live in the same way.

These registers are defined by the unwinder and so in reality they
are live on entry to the EH receiver.  But definitions can only happen
in blocks, not on edges, so for liveness purposes we use artificial
definitions at the start of the EH receiver.  process_bb_lives should
therefore model the effect of a definition, not a plain use.

2020-04-06  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR rtl-optimization/92989
	* lra-lives.c (process_bb_lives): Do not treat eh_return data
	registers as being live at the beginning of the EH receiver.

	PR libstdc++/94498
	* include/bits/char_traits.h (__gnu_cxx::char_traits::move): Make it
	usable in constant expressions for C++20.
	(__gnu_cxx::char_traits::copy, __gnu_cxx::char_traits::assign): Add
	_GLIBCXX20_CONSTEXPR.
	(std::char_traits<char>, std::char_traits<wchar_t>)
	(std::char_traits<char8_t>): Make move, copy and assign usable in
	constant expressions for C++20.
	(std::char_traits<char16_t>, std::char_traits<char32_t>): Make move
	and copy usable in constant expressions for C++20.
	* include/std/string_view (basic_string_view::copy): Add
	_GLIBCXX20_CONSTEXPR.
	* testsuite/21_strings/basic_string_view/operations/copy/char/
	constexpr.cc: New test.
	* testsuite/21_strings/basic_string_view/operations/copy/wchar_t/
	constexpr.cc: New test.

Here we crash in the gimplifier because gimplify_init_ctor_eval doesn't
expect null indexes for a constructor:

      /* ??? Here's to hoping the front end fills in all of the indices,
         so we don't have to figure out what's missing ourselves.  */
      gcc_assert (purpose);

The indexes weren't filled because we never called reshape_init: for
a constructor that represents parenthesized initialization of an
aggregate we don't allow brace elision or designated initializers.

	PR c++/94155 - crash in gimplifier with paren init of aggregates.
	* init.c (build_vec_init): Fill in indexes.

	* g++.dg/cpp2a/paren-init22.C: New test.

	* doc/xml/manual/appendix_contributing.xml: Refer to Git
	documentation instead of Subversion.  Switch to https.
	* doc/html/manual/appendix_contributing.html: Regenerate.

Try to keep tests order by distinct number (and with a short
descriptive name appended).

2020-04-05  Iain Sandoe  <iain@sandoe.co.uk>

	* g++.dg/coroutines/torture/co-await-14-template-traits.C: Rename...
	* g++.dg/coroutines/torture/co-await-16-template-traits.C: to this.
	* g++.dg/coroutines/torture/co-await-15-capture-comp-ref.C: Rename..
	* g++.dg/coroutines/torture/co-await-17-capture-comp-ref.C: to this.

	* extend.texi: Add free to list of ISO C90 functions that
	are recognized by the compiler.

Microblaze: Fixed missing save of r18 in fast_interrupt. Register 18 is used as a clobber register, and must be stored when entering a fast_interrupt. Before this fix, register 18 was only saved if it was used directly in the interrupt function.

    However, if the fast_interrupt function called a function that used
    r18, the register would not be saved, and thus be mangled
    upon returning from the interrupt.

	* config/microblaze/microblaze.c (microblaze_must_save_register): Check
	for fast_interrupt.

Microblaze: Modified trap instruction There is a bug in trap instruction generation. Instead of "bri 0" instruction "brki r0, -1" was used, corrected it now.

        * gcc/config/microblaze/microblaze.md (trap): Update output pattern.

        * gcc.target/microblaze/others/builtin-trap.c: Update expected output.