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riscv-gcc-1
Commit d2ce75fe by Andre Simoes Dias Vieira Committed by Andre Vieira
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arm: MVE Fix immediate constraints on some vector instructions 

Hi,

This patch fixes the immediate checks on vcvt and vqshr(u)n[bt] instructions.
It also removes the 'arm_mve_immediate_check' as the check was wrong and the
error message is not much better than the constraint one, which albeit isn't
great either.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.c (arm_mve_immediate_check): Removed.
	* config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
	(mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
	 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
	 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
	 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
	 mve_vqshruntq_m_n_s*): Fixed immediate constraints.

gcc/testsuite/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c: New test.
parent 094bc16b
Showing with 94 additions and 41 deletions
gcc/ChangeLog
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.c (arm_mve_immediate_check): Removed.
* config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
(mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
mve_vqshruntq_m_n_s*): Fixed immediate constraints.
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
......
gcc/config/arm/arm.c
......@@ -32693,31 +32693,6 @@ arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
return true;
}
/* To check op's immediate values matches the mode of the defined insn. */
bool
arm_mve_immediate_check (rtx op, machine_mode mode, bool val)
{
if (val)
{
if (((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 7)
&& (mode == E_V16QImode))
|| ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 15)
&& (mode == E_V8HImode))
|| ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 31)
&& (mode == E_V4SImode)))
return true;
}
else
{
if (((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 7)
&& (mode == E_V8HImode))
|| ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 15)
&& (mode == E_V4SImode)))
return true;
}
return false;
}
/* Can output mi_thunk for all cases except for non-zero vcall_offset
in Thumb1. */
static bool
......
gcc/config/arm/mve.md
......@@ -401,8 +401,10 @@
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
(VCTP32Q_M "32") (VCTP64Q_M "64")])
(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
(V4SI "mve_imm_32")])
(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
(V4SI "mve_imm_32")
(V8HF "mve_imm_16") (V4SF "mve_imm_32")])
(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")
(V8HF "Rd") (V4SF "Rf")])
(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
......@@ -1330,7 +1332,7 @@
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
(match_operand:SI 2 "mve_imm_16" "Rd")]
(match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
VCVTQ_N_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
......@@ -1389,7 +1391,7 @@
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
(match_operand:SI 2 "mve_imm_16" "Rd")]
(match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
VCVTQ_N_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
......@@ -5484,7 +5486,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")]
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
VQSHRNBQ_N))
]
"TARGET_HAVE_MVE"
......@@ -5500,7 +5502,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")]
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
VQSHRNTQ_N))
]
"TARGET_HAVE_MVE"
......@@ -5516,7 +5518,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")]
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
VQSHRUNBQ_N_S))
]
"TARGET_HAVE_MVE"
......@@ -5532,7 +5534,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")]
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
VQSHRUNTQ_N_S))
]
"TARGET_HAVE_MVE"
......@@ -5868,7 +5870,7 @@
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
(match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_16" "Rd")
(match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VCVTQ_M_N_FROM_F))
]
......@@ -6030,7 +6032,7 @@
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_16" "Rd")
(match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VCVTQ_M_N_TO_F))
]
......@@ -7134,11 +7136,11 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VQSHRNBQ_M_N))
]
"TARGET_HAVE_MVE && arm_mve_immediate_check (operands[3], <MODE>mode, 0)"
"TARGET_HAVE_MVE"
"vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -7151,7 +7153,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VQSHRNTQ_M_N))
]
......@@ -7440,7 +7442,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VQRSHRUNTQ_M_N_S))
]
......@@ -7457,7 +7459,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VQSHRUNBQ_M_N_S))
]
......@@ -7474,7 +7476,7 @@
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")
(match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VQSHRUNTQ_M_N_S))
]
......
gcc/testsuite/ChangeLog
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c: New test.
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/mve/intrinsics/mve_load_from_array.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vector_float.c: Remove
scan-assembler.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c 0 → 100644
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t u8;
int8x16_t s8;
uint16x8_t u16;
int16x8_t s16;
uint32x4_t u32;
int32x4_t s32;
float16x8_t f16;
float32x4_t f32;
#define MACRO_VCVT_NAME(__to1,__from1) \
vcvtq_n_##__to1 ## _ ##__from1
#define MACRO_VCVT_NAME_P(__to1,__from1) \
vcvtq_m_n_##__to1 ## _ ##__from1
#define VCVT_TEST(to,from,val) \
to = MACRO_VCVT_NAME(to,from) (from, val); \
to = MACRO_VCVT_NAME_P(to,from) (to, from, val, p);
#define VQSHRN_TEST(to,from,val) \
to = vqshrnbq (to, from, val); \
to = vqshrntq (to, from, val); \
to = vqshrnbq_m (to, from, val, p); \
to = vqshrntq_m (to, from, val, p); \
#define VQSHRUN_TEST(to,from,val) \
to = vqshrunbq (to, from, val); \
to = vqshruntq (to, from, val); \
to = vqshrunbq_m (to, from, val, p); \
to = vqshruntq_m (to, from, val, p); \
void test (mve_pred16_t p)
{
VCVT_TEST(f16,s16,16)
VCVT_TEST(f16,u16,16)
VCVT_TEST(f32,s32,32)
VCVT_TEST(f32,u32,32)
VCVT_TEST(u16,f16,16)
VCVT_TEST(s16,f16,16)
VCVT_TEST(u32,f32,32)
VCVT_TEST(s32,f32,32)
VCVT_TEST(f16,s16,1)
VCVT_TEST(f16,u16,1)
VCVT_TEST(f32,s32,1)
VCVT_TEST(f32,u32,1)
VCVT_TEST(u16,f16,1)
VCVT_TEST(s16,f16,1)
VCVT_TEST(u32,f32,1)
VCVT_TEST(s32,f32,1)
VQSHRN_TEST(u8, u16, 8)
VQSHRN_TEST(s8, s16, 8)
VQSHRN_TEST(u16, u32, 16)
VQSHRN_TEST(s16, s32, 16)
VQSHRUN_TEST(u8, s16, 8)
VQSHRUN_TEST(u16, s32, 16)
}
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