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riscv-gcc-1
Commit 9ce780ef by Andre Simoes Dias Vieira Committed by Andre Vieira
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arm: MVE: Fix v[id]wdup's 

This patch fixes v[id]wdup intrinsics. They had two issues:
1) the predicated versions did not link the incoming inactive vector parameter
to the output
2) The backend didn't enforce the wrap limit operand be in an odd register.

1) was fixed like we did for all other predicated intrinsics
2) requires a temporary hack where we pass the value in the top end of DImode
operand. The proper fix would be to add a register CLASS but this interacted
badly with other existing targets codegen.  We will look to fix this properly in GCC 11.

gcc/ChangeLog:
2020-04-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
	* config/arm/mve/md: Fix v[id]wdup patterns.
parent b094133c
Showing with 28 additions and 22 deletions
gcc/ChangeLog
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
* config/arm/mve/md: Fix v[id]wdup patterns.
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.c (output_move_neon): Deal with label + offset cases.
* config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
......
gcc/config/arm/mve.md
......@@ -9853,7 +9853,7 @@
(define_expand "mve_vdwdupq_n_u<mode>"
[(match_operand:MVE_2 0 "s_register_operand")
(match_operand:SI 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:DI 2 "s_register_operand")
(match_operand:SI 3 "mve_imm_selective_upto_8")]
"TARGET_HAVE_MVE"
{
......@@ -9870,7 +9870,7 @@
(define_expand "mve_vdwdupq_wb_u<mode>"
[(match_operand:SI 0 "s_register_operand")
(match_operand:SI 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:DI 2 "s_register_operand")
(match_operand:SI 3 "mve_imm_selective_upto_8")
(unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_HAVE_MVE"
......@@ -9888,16 +9888,16 @@
(define_insn "mve_vdwdupq_wb_u<mode>_insn"
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
(match_operand:SI 3 "s_register_operand" "r")
(subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
VDWDUPQ))
(set (match_operand:SI 1 "s_register_operand" "=e")
(unspec:SI [(match_dup 2)
(match_dup 3)
(subreg:SI (match_dup 3) 4)
(match_dup 4)]
VDWDUPQ))]
"TARGET_HAVE_MVE"
"vdwdup.u%#<V_sz_elem>\t%q0, %2, %3, %4"
"vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
)
;;
......@@ -9907,7 +9907,7 @@
[(match_operand:MVE_2 0 "s_register_operand")
(match_operand:MVE_2 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:SI 3 "s_register_operand")
(match_operand:DI 3 "s_register_operand")
(match_operand:SI 4 "mve_imm_selective_upto_8")
(match_operand:HI 5 "vpr_register_operand")]
"TARGET_HAVE_MVE"
......@@ -9927,7 +9927,7 @@
[(match_operand:SI 0 "s_register_operand")
(match_operand:MVE_2 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:SI 3 "s_register_operand")
(match_operand:DI 3 "s_register_operand")
(match_operand:SI 4 "mve_imm_selective_upto_8")
(match_operand:HI 5 "vpr_register_operand")]
"TARGET_HAVE_MVE"
......@@ -9945,22 +9945,22 @@
;;
(define_insn "mve_vdwdupq_m_wb_u<mode>_insn"
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w")
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
(match_operand:SI 3 "s_register_operand" "1")
(match_operand:SI 4 "s_register_operand" "r")
(subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
(match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
(match_operand:HI 6 "vpr_register_operand" "Up")]
VDWDUPQ_M))
(set (match_operand:SI 1 "s_register_operand" "=e")
(unspec:SI [(match_dup 2)
(match_dup 3)
(match_dup 4)
(subreg:SI (match_dup 4) 4)
(match_dup 5)
(match_dup 6)]
VDWDUPQ_M))
]
"TARGET_HAVE_MVE"
"vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %4, %5"
"vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -9970,7 +9970,7 @@
(define_expand "mve_viwdupq_n_u<mode>"
[(match_operand:MVE_2 0 "s_register_operand")
(match_operand:SI 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:DI 2 "s_register_operand")
(match_operand:SI 3 "mve_imm_selective_upto_8")]
"TARGET_HAVE_MVE"
{
......@@ -9987,7 +9987,7 @@
(define_expand "mve_viwdupq_wb_u<mode>"
[(match_operand:SI 0 "s_register_operand")
(match_operand:SI 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:DI 2 "s_register_operand")
(match_operand:SI 3 "mve_imm_selective_upto_8")
(unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_HAVE_MVE"
......@@ -10005,16 +10005,16 @@
(define_insn "mve_viwdupq_wb_u<mode>_insn"
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
(match_operand:SI 3 "s_register_operand" "r")
(subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
VIWDUPQ))
(set (match_operand:SI 1 "s_register_operand" "=e")
(unspec:SI [(match_dup 2)
(match_dup 3)
(subreg:SI (match_dup 3) 4)
(match_dup 4)]
VIWDUPQ))]
"TARGET_HAVE_MVE"
"viwdup.u%#<V_sz_elem>\t%q0, %2, %3, %4"
"viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
)
;;
......@@ -10024,7 +10024,7 @@
[(match_operand:MVE_2 0 "s_register_operand")
(match_operand:MVE_2 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:SI 3 "s_register_operand")
(match_operand:DI 3 "s_register_operand")
(match_operand:SI 4 "mve_imm_selective_upto_8")
(match_operand:HI 5 "vpr_register_operand")]
"TARGET_HAVE_MVE"
......@@ -10044,7 +10044,7 @@
[(match_operand:SI 0 "s_register_operand")
(match_operand:MVE_2 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:SI 3 "s_register_operand")
(match_operand:DI 3 "s_register_operand")
(match_operand:SI 4 "mve_imm_selective_upto_8")
(match_operand:HI 5 "vpr_register_operand")]
"TARGET_HAVE_MVE"
......@@ -10062,24 +10062,25 @@
;;
(define_insn "mve_viwdupq_m_wb_u<mode>_insn"
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w")
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
(match_operand:SI 3 "s_register_operand" "1")
(match_operand:SI 4 "s_register_operand" "r")
(subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
(match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
(match_operand:HI 6 "vpr_register_operand" "Up")]
VIWDUPQ_M))
(set (match_operand:SI 1 "s_register_operand" "=e")
(unspec:SI [(match_dup 2)
(match_dup 3)
(match_dup 4)
(subreg:SI (match_dup 4) 4)
(match_dup 5)
(match_dup 6)]
VIWDUPQ_M))
]
"TARGET_HAVE_MVE"
"vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %4, %5"
"vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
(define_expand "mve_vstrwq_scatter_base_wb_<supf>v4si"
[(match_operand:V4SI 0 "s_register_operand" "=w")
(match_operand:SI 1 "mve_vldrd_immediate" "Ri")
......
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