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  1. 12 Aug, 2016 3 commits
    • [PR55641] drop spurious const_type from reference_type variables · 71e1a6a4 
      Although C++ reference types, denoted by DW_TAG_reference_type in
DWARFv2+ debug info, are unchangeable, we output names of reference type
with DW_TAG_const_type, because internally we mark such variables as
TREE_READONLY.  That's an internal implementation detail that shouldn't
leak to debug information.  This patch fixes this.

for  gcc/ChangeLog

	PR debug/55641
	* dwarf2out.c (decl_quals): Don't map TREE_READONLY to
	TYPE_QUAL_CONST in reference-typed decls.

for  gcc/testsuite/ChangeLog

	PR debug/55641
	* g++.dg/debug/dwarf2/ref-1.C: New.

From-SVN: r239402
      Alexandre Oliva committed
    • [PR49366] emit loc exprs for C++ non-virtual pmf template value parms · 8aaf799b 
      We used to emit, in debug information, the values bound to pointer to
member function template parameters only when they were NULL or
virtual member functions, because those can be represented with
DW_AT_const_value.

In order to represent the symbolic pointer to member function
constants for non-virtual member functions, we'd need to be able to
emit relocations for part of DW_AT_const_value, which we don't.  The
more viable alternative is to use DW_AT_location to represent such
values, as slated for inclusion in DWARFv5, according to
<URL:http://www.dwarfstd.org/ShowIssue.php?issue=130412.1>.

With this patch, when we can't emit a DW_AT_const_value, we emit each
"member" of the pointer to member function "record" as a
DW_OP_stack_value DW_OP_piece, as long as the referenced member
function is output in the same translation unit, otherwise we'd get
relocations to external symbols, something to avoid in debug sections.


for  gcc/ChangeLog

	PR debug/49366
	* dwarf2out.c (loc_list_from_tree_1): Expand some CONSTRUCTORs
	in DW_OP_pieces, just enough to handle pointers to member
	functions.
	(gen_remaining_tmpl_value_param_die_attribute): Use a location
	expression on DWARFv5 if a constant value doesn't work.

for  gcc/testsuite/ChangeLog

	PR debug/49366
	* g++.dg/debug/dwarf2/template-params-12.H: New.
	* g++.dg/debug/dwarf2/template-params-12f.C: New.
	* g++.dg/debug/dwarf2/template-params-12g.C: New.
	* g++.dg/debug/dwarf2/template-params-12n.C: New.
	* g++.dg/debug/dwarf2/template-params-12s.C: New.
	* g++.dg/debug/dwarf2/template-params-12u.C: New.
	* g++.dg/debug/dwarf2/template-params-12v.C: New.
	* g++.dg/debug/dwarf2/template-params-12w.C: New.

From-SVN: r239401
      Alexandre Oliva committed
    • Daily bump. · df5b19dc 
      From-SVN: r239400
      GCC Administrator committed
  3. 11 Aug, 2016 25 commits
  5. 10 Aug, 2016 12 commits
    • missed from last commit · 763a282e 
      From-SVN: r239343
      Alan Modra committed
    • [LRA] Reload of slow mems · 2e186411 
      pr71680.c -m64 -O1 -mlra, ira output showing two problem insns.
(insn 7 5 26 3 (set (reg:SI 159 [ a ])
        (mem/c:SI (reg/f:DI 158) [1 a+0 S4 A8])) pr71680.c:13 464 {*movsi_internal1}
     (expr_list:REG_EQUIV (mem/c:SI (reg/f:DI 158) [1 a+0 S4 A8])
        (nil)))
(insn 26 7 27 3 (set (reg:DI 162)
        (unspec:DI [
                (fix:SI (subreg:SF (reg:SI 159 [ a ]) 0))
            ] UNSPEC_FCTIWZ)) pr71680.c:13 372 {fctiwz_sf}
     (expr_list:REG_DEAD (reg:SI 159 [ a ])
        (nil)))
Insn 26 requires that reg 159 be of class FLOAT_REGS.

first lra action:
deleting insn with uid = 7.
Changing pseudo 159 in operand 1 of insn 26 on equiv [r158:DI]
      Creating newreg=164, assigning class ALL_REGS to subreg reg r164
   26: r162:DI=unspec[fix(r164:SI#0)] 7
      REG_DEAD r159:SI
    Inserting subreg reload before:
   30: r164:SI=[r158:DI]
[snip]
      Change to class FLOAT_REGS for r164

Well, that didn't do much.  lra tried the equiv mem, found that didn't
work, and had to reload.  Effectively getting back to the two original
insns but r159 replaced with r164.  simplify_operand_subreg did not do
anything in this case because SLOW_UNALIGNED_ACCESS was true (wrongly
for power8, but that's beside the point).  So now we have, using
abbreviated rtl notation:
r164:SI=[r158:DI]
r162:DI=unspec[fix(r164:SI)]
The problem here is that the first insn isn't valid, due to the rs6000
backend not supporting SImode in fprs, and r164 must be an fpr to make
the second insn valid.

next lra action:
      Creating newreg=165 from oldreg=164, assigning class GENERAL_REGS to r165
   30: r165:SI=[r158:DI]
    Inserting insn reload after:
   31: r164:SI=r165:SI
so now we have
r165:SI=[r158:DI]
r164:SI=r165:SI
r162:DI=unspec[fix(r164:SI)]

This ought to be good on power8, except for one little thing.
r165 is GENERAL_REGS so the first insn is good, a gpr load from mem.
r164 is FLOAT_REGS, making the last insn good, a fctiwz.
The second insn ought to be a sldi, mtvsrd, xscvspdpn combination, but
that is only supported for SFmode.  So lra continue on reloading the
second insn, but in vain because it never tries anything other than
SImode and as noted above, SImode is not valid in fprs.

What this patch does is arrange to emit the two reloads needed for the
SLOW_UNALIGNED_ACCESS case at once, moving the subreg to the second
insn in order to switch modes, producing:

r164:SI=[r158:DI]
r165:SF=r164:SI#0
r162:DI=unspec[fix(r165:SF)]

I've also tidied a couple of other things:
1) "old" is unnecessary as it duplicated "operand".
2) Rejecting mem subregs due to SLOW_UNALIGNED_ACCESS only makes sense
if the original mode was not slow.

	PR target/71680
	* lra-constraints.c (simplify_operand_subreg): Allow subreg
	mode for mem when SLOW_UNALIGNED_ACCESS if inner mode is also
	slow.  Emit two reloads for slow mem case, first loading in
	fast innermode, then converting to required mode.
testsuite/
	* gcc.target/powerpc/pr71680.c: New.

From-SVN: r239342
      Alan Modra committed
    • * c-cppbuiltin.c (c_cpp_builtins): Define __cpp_if_constexpr. · 452df4a4 
      From-SVN: r239340
      Jason Merrill committed
    • Implement C++17 constexpr if. · 99f9d4b1 
      	* cp-tree.h (IF_STMT_CONSTEXPR_P): New.
	* name-lookup.c (push_to_top_level, pop_from_top_level_1): Handle it.
	* parser.h (struct cp_parser): Add in_discarded_stmt field.
	* parser.c (cp_parser_selection_statement): Handle 'if constexpr'.
	(cp_parser_jump_statement): Avoid deducing from a discarded return.
	* pt.c (tsubst_expr): Only instantiate taken branch of constexpr if.
	* semantics.c (begin_if_stmt): Set the binding level this_entity.
	(finish_if_stmt_cond): Require the condition of a
	constexpr if to be constant.
	* decl.c (level_for_constexpr_if): New.
	(named_label_entry): Add in_constexpr_if field.
	(poplevel_named_label_1): Set it.
	(check_goto): Check it.
	(check_previous_goto_1): Check level_for_constexpr_if.

From-SVN: r239338
      Jason Merrill committed
    • altivec.h (vec_extract_exp): New macro. · e9e6d4f6 
      gcc/ChangeLog:

2016-08-10  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.h (vec_extract_exp): New macro.
	(vec_extract_sig): New macro.
	(vec_insert_exp): New macro.
	(vec_test_data_class): New macro.
	(scalar_extract_exp): New macro.
	(scalar_extract_sig): New macro.
	(scalar_insert_exp): New macro.
	(scalar_test_data_class): New macro.
	(scalar_test_neg): New macro.
	(scalar_cmp_exp_gt): New macro.
	(scalar_cmp_exp_lt): New macro.
	(scalar_cmp_exp_eq): New macro.
	(scalar_cmp_exp_unordered): New macro.
	* config/rs6000/predicates.md (u7bit_cint_operand): New predicate
	to enforce constraint that operand is a 7-bit unsigned literal.
	* config/rs6000/rs6000-builtin.def (BU_P9V_64BIT_VSX_1): New macro
	for power9 built-ins.
	(BU_P9V_VSX_2): Likewise.
	(BU_P9V_64BIT_VSX_2): Likewise.
	(VSEEDP): Add scalar extract exponent support.
	(VSEESP): Add scalar extract signature support.
	(VSTDCNDP): Add scalar test negative support.
	(VSTDCNSP): Likewise.
	(VSIEDP): Add scalar insert exponent support.
	(VSCEDPGT): Add scalar compare exponent greater than support.
	(VSCEDPLT): Add scalar compare exponent less than support.
	(VSCEDPEQ): Add scalar compare exponent test-for-equality support.
	(VSCEDPUO): Add scalar compare exponent test-for-unordered support.
	(VSTDCDP): Add scalar test data class support.
	(VSTDCSP): Likewise.
	(VSEEDP): Add overload support for scalar extract exponent
	operation.
	(VSESDP): Add overload support for scalar extract signature
	operation.
	(VSTDCN): Add overload support for scalar test negative
	operation.
	(VSTDCNDP): Add overload support for scalar test negative
	operation.
	(VSTDCNSP): Add overload support for scalar test negative
	operation.
	(VSIEDP): Add overload support for scalar insert exponent
	operation.
	(VSTDC): Add overload support for scalar test data class
	operation.
	(VSTDCDP): Add overload support for scalar test data class
	operation.
	(VSTDCSP): Add overload support for scalar test data class
	opreation.
	(VSCEDPGT): Add overload support for scalar compare exponent
	greater than operation.
	(VSCEDPLT): Add overload support for scalar compare exponent
	less than operation.
	(VSCEDPEQ): Add overload support for scalar compare exponent
	test-for-equality operation.
	(VSCEDPUO): Add overload support for scalar compare exponent
	test-for-unordered operation.
	(VEEDP): Add vector extract exponent support.
	(VEESP): Likewise.
	(VESDP): Add vector extract significand support.
	(VESSP): Likewise.
	(VIEDP): Add vector insert exponent support.
	(VIESP): Likewise.
	(VTDCDP): Add vector test data class support.
	(VTDCSP): Likewise.
	(VES): Add overload support for vector extract significand operation.
	(VESDP): Likewise.
	(VESSP): Likewise
	(VEE): Add overload support for vector extract exponent operation.
	(VEEDP): Likewise.
	(VEESP): Likewise.
	(VTDC): Add overload support for vector test data class operation.
	(VTDCDP): Likewise.
	(VTDCSP): Likewise.
	(VIE): Add overload support for vector insert exponent operation.
	(VIEDP): Likewise.
	(VIESP): Likewise.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	overloaded binary floating point functions.
	(altivec_resolve_overloaded_builtin): Improve error messages to
	distinguish between functions not supported in the current
	compiler configuration and functions that were invoked with an
	invalid parameter combination, and include the built-in function
	name in both error messages.
	* config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_name):
	New prototype.
	* config/rs6000/rs6000.c (rs6000_overloaded_builtin_name): New
	function.
	(rs6000_expand_binop_builtin): Add check to enforce that argument
	2 of the test data class operations is a 7-bit unsigned literal.
	(rs6000_invalid_builtin): Add code to issue an error message if a
	built-in function that requires the power9_vector and -m32
	command-line options is compiled without these options.
	* config/rs6000/vsx.md (UNSPEC_VSX_SXEXPDP): New value.
	(UNSPEC_VSX_SXSIGDP): New value.
	(UNSPEC_VSX_SXSIGPDP): New value.
	(UNSPEC_VSX_SIEXPDP): New value.
	(UNSPEC_VSX_SCMPEXPDP): New value.
	(UNSPEC_VSX_STSTDC): New value.
	(UNSPEC_VSX_VXEXP): New value.
	(UNSPEC_VSX_VXSIG): New value.
	(UNSPEC_VSX_VIEXP): New value.
	(UNSPEC_VSX_VTSTDC): New value.
	(xsxexpdp): New insn for scalar extract exponent.
	(xsxsigdp): New insn for scalar extract significand.
	(xsiexpdp): New insn for scalar insert exponent.
	(xscmpexpdp_<code>): New expansion for scalar compare exponents.
	(*xscmpexpdp): New insn for scalar compare exponents.
	(xststdc<Fvsx): New expansion for both single- and
	double-precision scalar test data class operations.
	(xststdcneg<Fvsx>): New expansion for both single- and
	double-precision scalar test for negative value operations.
	(*xststdc<Fvsx>): New insn for scalar test data class
	operation.
	(xvxexp<VSs>): New insn for single- and double-precision
	vector extract exponent operation.
	(xvxsig<VSs>): New insn for single- and double-precision
	vector extract significand operation.
	(xviexp<VSs>): New insn for single- and double-precision
	vector insert exponent operation.
	(xvtstdc<VSs>): New insn for single- and double-precision
	vector test data class operation.
	* doc/extend.texi (PowerPC AltiVec Built-in Functions): Document
	built-in functions to represent the Power9 binary floating-point
	support instructions.

gcc/testsuite/ChangeLog:

2016-08-10  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/bfp/bfp.exp: New file.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-extract-exp-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-extract-exp-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-extract-exp-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-extract-sig-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-extract-sig-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-insert-exp-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-insert-exp-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-3.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-4.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-5.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-6.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-7.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-neg-0.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-neg-1.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-neg-2.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-neg-3.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-exp-0.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-exp-1.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-exp-2.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-exp-3.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-sig-0.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-sig-1.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-sig-2.c: New test.
	* gcc.target/powerpc/bfp/vec-extract-sig-3.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-0.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-1.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-2.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-3.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-0.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-1.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-2.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-3.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-4.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-5.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-6.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-7.c: New test.

From-SVN: r239334
      Kelvin Nilsen committed
    • compiler: annotate or fix fall through cases in switch statements · 4cc1fc4f 
          
    A new GCC warning, -Wimplicit-fallthrough, detected these three cases
    where a switch case falls through to another.  One of them looks like
    a bug, so I fixed it; the two other look like intended fall throughs
    so I just added a "fall through" comment to suppress the GCC warning.
    
    Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu.
    
    Reviewed-on: https://go-review.googlesource.com/26695

From-SVN: r239332
      Ian Lance Taylor committed
    • * doc/sourcebuild.texi (@item vect_cond_mixed): New item. · 5a02adf6 
      From-SVN: r239330
      Bin Cheng committed
    • target-supports.exp (check_effective_target_vect_cond_mixed): Add aarch64*-*-*. · 9c8eabea 
      	gcc/testsuite
	* lib/target-supports.exp (check_effective_target_vect_cond_mixed):
	Add aarch64*-*-*.

From-SVN: r239329
      Bin Cheng committed
    • iterators.md (V_cmp_mixed, [...]): New. · 6c553b76 
      	* config/aarch64/iterators.md (V_cmp_mixed, v_cmp_mixed): New.
	* config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): Call
	gen_vcondv2div2di instead of gen_aarch64_vcond_internalv2div2di.
	(aarch64_vcond_internal<mode><mode>): Delete pattern.
	(aarch64_vcond_internal<VDQF_COND:mode><VDQF:mode>): Ditto.
	(vcond<v_cmp_result><mode>): Ditto.
	(vcond<mode><mode>): Re-implement using vec_cmp and vcond_mask.
	(vcondu<mode><mode>): Ditto.
	(vcond<v_cmp_mixed><mode>): New pattern.
	(vcondu<mode><v_cmp_mixed>): New pattern.
	(aarch64_cmtst<mode>): Revise comment using aarch64_vcond instead
	of aarch64_vcond_internal.

	gcc/testsuite
	* gcc.target/aarch64/simd/vcond-ne.c: New test.

From-SVN: r239328
      Bin Cheng committed
    • aarch64-simd.md (vec_cmp<mode><mode>): New pattern. · 45d569f3 
      	* config/aarch64/aarch64-simd.md (vec_cmp<mode><mode>): New pattern.
	(vec_cmp<mode><v_cmp_result>): New pattern.
	(vec_cmpu<mode><mode>): New pattern.
	(vcond_mask_<mode><v_cmp_result>): New pattern.

Co-Authored-By: Bin Cheng <bin.cheng@arm.com>
Co-Authored-By: Renlin Li <renlin.li@arm.com>

From-SVN: r239327
      Alan Lawrence committed
    • re PR middle-end/71734 (FAIL: libgomp.fortran/simd4.f90 -O3 -g execution test) · ff4fa993 
      Fix PR tree-optimization/71734

2016-08-10  Yuri Rumyantsev  <ysrumyan@gmail.com>

	PR tree-optimization/71734
	* tree-ssa-loop-im.c (ref_indep_loop_p): Add new argument
	REF_LOOP, invoke ref_indep_loop_p_1.
	(outermost_indep_loop): Pass LOOP argumnet where REF was defined
	to ref_indep_loop_p.
	(ref_indep_loop_p_1): Fix commentary, add argument REF_LOOP,
	combine it with ref_indep_lopp_p_2, update SAFELEN if only REF
	is inside LOOP, do not cache dpendence value for loops with
	non-zero SAFELEN.
	(ref_indep_loop_p_2): Delete function.
	(can_sm_ref_p): Pass LOOP as additional argument to
	ref_indep_loop_p.

From-SVN: r239326
      Yuri Rumyantsev committed
    • re PR target/72853 (gcc/testsuite/gcc.c-torture/execute/20021120-1.c generates… · a0883b08 
      re PR target/72853 (gcc/testsuite/gcc.c-torture/execute/20021120-1.c generates incorrect stxssp op with -mcpu=power9)

[gcc]
2016-08-10  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/72853
	* config/rs6000/rs6000.c (mem_operand_ds_form): Add check for op
	being an offsettable address.

[gcc/testsuite]
2016-08-10  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/72853
	* gcc.target/powerpc/pr72853.c: New test.

From-SVN: r239325
      Michael Meissner committed