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riscv-gcc-1
Commit 5a02adf6 by Bin Cheng Committed by Bin Cheng
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* doc/sourcebuild.texi (@item vect_cond_mixed): New item. 

From-SVN: r239330
parent 9c8eabea
Showing with 8 additions and 0 deletions
gcc/ChangeLog
2016-08-10 bin cheng <bin.cheng@arm.com>
* doc/sourcebuild.texi (@item vect_cond_mixed): New item.
2016-08-10 Alan Lawrence <alan.lawrence@arm.com> 2016-08-10 Alan Lawrence <alan.lawrence@arm.com>
Renlin Li <renlin.li@arm.com> Renlin Li <renlin.li@arm.com>
Bin Cheng <bin.cheng@arm.com> Bin Cheng <bin.cheng@arm.com>
......
gcc/doc/sourcebuild.texi
...@@ -1342,6 +1342,10 @@ Target supports Fortran @code{real} kinds larger than @code{real(8)}. ...@@ -1342,6 +1342,10 @@ Target supports Fortran @code{real} kinds larger than @code{real(8)}.
@item vect_condition @item vect_condition
Target supports vector conditional operations. Target supports vector conditional operations.
@item vect_cond_mixed
Target supports vector conditional operations where comparison operands
have different type from the value operands.
@item vect_double @item vect_double
Target supports hardware vectors of @code{double}. Target supports hardware vectors of @code{double}.
......
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