rtl.def

/* This file contains the definitions and documentation for the
   Register Transfer Expressions (rtx's) that make up the
   Register Transfer Language (rtl) used in the Back End of the GNU compiler.
   Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
   Free Software Foundation, Inc.

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */


/* Expression definitions and descriptions for all targets are in this file.
   Some will not be used for some targets.

   The fields in the cpp macro call "DEF_RTL_EXPR()"
   are used to create declarations in the C source of the compiler.

   The fields are:

   1.  The internal name of the rtx used in the C source.
   It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
   By convention these are in UPPER_CASE.

   2.  The name of the rtx in the external ASCII format read by
   read_rtx(), and printed by print_rtx().
   These names are stored in rtx_name[].
   By convention these are the internal (field 1) names in lower_case.

   3.  The print format, and type of each rtx->fld[] (field) in this rtx.
   These formats are stored in rtx_format[].
   The meaning of the formats is documented in front of this array in rtl.c
   
   4.  The class of the rtx.  These are stored in rtx_class and are accessed
   via the GET_RTX_CLASS macro.  They are defined as follows:

     "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
     "<" an rtx code for a comparison (e.g, EQ, NE, LT)
     "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
     "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
     "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
     "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
     "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
     "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
     "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
     "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
     "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
     "x" everything else
     
   */

/* ---------------------------------------------------------------------
   Expressions (and "meta" expressions) used for structuring the
   rtl representation of a program.
   --------------------------------------------------------------------- */

/* an expression code name unknown to the reader */
DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')

/* (NIL) is used by rtl reader and printer to represent a null pointer.  */

DEF_RTL_EXPR(NIL, "nil", "*", 'x')

/* ---------------------------------------------------------------------
   Expressions used in constructing lists.
   --------------------------------------------------------------------- */

/* a linked list of expressions */
DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')

/* a linked list of instructions.
   The insns are represented in print by their uids.  */
DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')

/* ----------------------------------------------------------------------
   Expression types for machine descriptions.
   These do not appear in actual rtl code in the compiler.
   ---------------------------------------------------------------------- */

/* Appears only in machine descriptions.
   Means use the function named by the second arg (the string)
   as a predicate; if matched, store the structure that was matched
   in the operand table at index specified by the first arg (the integer).
   If the second arg is the null string, the structure is just stored.

   A third string argument indicates to the register allocator restrictions
   on where the operand can be allocated.

   If the target needs no restriction on any instruction this field should
   be the null string.

   The string is prepended by:
   '=' to indicate the operand is only written to.
   '+' to indicate the operand is both read and written to.

   Each character in the string represents an allocable class for an operand.
   'g' indicates the operand can be any valid class.
   'i' indicates the operand can be immediate (in the instruction) data.
   'r' indicates the operand can be in a register.
   'm' indicates the operand can be in memory.
   'o' a subset of the 'm' class.  Those memory addressing modes that
       can be offset at compile time (have a constant added to them).

   Other characters indicate target dependent operand classes and
   are described in each target's machine description.

   For instructions with more than one operand, sets of classes can be
   separated by a comma to indicate the appropriate multi-operand constraints.
   There must be a 1 to 1 correspondence between these sets of classes in
   all operands for an instruction.
   */
DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')

/* Appears only in machine descriptions.
   Means match a SCRATCH or a register.  When used to generate rtl, a
   SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
   the desired mode and the first argument is the operand number.
   The second argument is the constraint.  */
DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')

/* Appears only in machine descriptions.
   Means match only something equal to what is stored in the operand table
   at the index specified by the argument.  */
DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')

/* Appears only in machine descriptions.
   Means apply a predicate, AND match recursively the operands of the rtx.
   Operand 0 is the operand-number, as in match_operand.
   Operand 1 is a predicate to apply (as a string, a function name).
   Operand 2 is a vector of expressions, each of which must match
   one subexpression of the rtx this construct is matching.  */
DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')

/* Appears only in machine descriptions.
   Means to match a PARALLEL of arbitrary length.  The predicate is applied
   to the PARALLEL and the initial expressions in the PARALLEL are matched.
   Operand 0 is the operand-number, as in match_operand.
   Operand 1 is a predicate to apply to the PARALLEL.
   Operand 2 is a vector of expressions, each of which must match the 
   corresponding element in the PARALLEL.  */
DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')

/* Appears only in machine descriptions.
   Means match only something equal to what is stored in the operand table
   at the index specified by the argument.  For MATCH_OPERATOR.  */
DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')

/* Appears only in machine descriptions.
   Means match only something equal to what is stored in the operand table
   at the index specified by the argument.  For MATCH_PARALLEL.  */
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')

/* Appears only in machine descriptions.
   Operand 0 is the operand number, as in match_operand.
   Operand 1 is the predicate to apply to the insn.  */
DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')

/* Appears only in machine descriptions.
   Defines the pattern for one kind of instruction.
   Operand:
   0: names this instruction.
      If the name is the null string, the instruction is in the
      machine description just to be recognized, and will never be emitted by
      the tree to rtl expander.
   1: is the pattern.
   2: is a string which is a C expression
      giving an additional condition for recognizing this pattern.
      A null string means no extra condition.
   3: is the action to execute if this pattern is matched.
      If this assembler code template starts with a * then it is a fragment of
      C code to run to decide on a template to use.  Otherwise, it is the
      template to use.
   4: optionally, a vector of attributes for this insn.
     */
DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')

/* Definition of a peephole optimization.
   1st operand: vector of insn patterns to match
   2nd operand: C expression that must be true
   3rd operand: template or C code to produce assembler output.
   4: optionally, a vector of attributes for this insn.
     */
DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')

/* Definition of a split operation.
   1st operand: insn pattern to match
   2nd operand: C expression that must be true
   3rd operand: vector of insn patterns to place into a SEQUENCE
   4th operand: optionally, some C code to execute before generating the
	insns.  This might, for example, create some RTX's and store them in
	elements of `recog_operand' for use by the vector of insn-patterns.
	(`operands' is an alias here for `recog_operand').   */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')

/* Definition of an insn and associated split.
   This is the concatenation, with a few modifications, of a define_insn
   and a define_split which share the same pattern.
   Operand:
   0: names this instruction.
      If the name is the null string, the instruction is in the
      machine description just to be recognized, and will never be emitted by
      the tree to rtl expander.
   1: is the pattern.
   2: is a string which is a C expression
      giving an additional condition for recognizing this pattern.
      A null string means no extra condition.
   3: is the action to execute if this pattern is matched.
      If this assembler code template starts with a * then it is a fragment of
      C code to run to decide on a template to use.  Otherwise, it is the
      template to use.
   4: C expression that must be true for split.  This may start with "&&"
      in which case the split condition is the logical and of the insn 
      condition and what follows the "&&" of this operand.
   5: vector of insn patterns to place into a SEQUENCE
   6: optionally, some C code to execute before generating the
	insns.  This might, for example, create some RTX's and store them in
	elements of `recog_operand' for use by the vector of insn-patterns.
	(`operands' is an alias here for `recog_operand').  
   7: optionally, a vector of attributes for this insn.  */
DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsssESV", 'x')

/* Definition of an RTL peephole operation.
   Follows the same arguments as define_split.  */
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')

/* Definition of a combiner pattern.
   Operands not defined yet.  */
DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')

/* Define how to generate multiple insns for a standard insn name.
   1st operand: the insn name.
   2nd operand: vector of insn-patterns.
	Use match_operand to substitute an element of `recog_operand'.
   3rd operand: C expression that must be true for this to be available.
	This may not test any operands.
   4th operand: Extra C code to execute before generating the insns.
	This might, for example, create some RTX's and store them in
	elements of `recog_operand' for use by the vector of insn-patterns.
	(`operands' is an alias here for `recog_operand').  */
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
   
/* Define a requirement for delay slots.
   1st operand: Condition involving insn attributes that, if true,
	        indicates that the insn requires the number of delay slots
		shown.
   2nd operand: Vector whose length is the three times the number of delay
		slots required.
	        Each entry gives three conditions, each involving attributes.
		The first must be true for an insn to occupy that delay slot
		location.  The second is true for all insns that can be
		annulled if the branch is true and the third is true for all
		insns that can be annulled if the branch is false. 

   Multiple DEFINE_DELAYs may be present.  They indicate differing
   requirements for delay slots.  */
DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')

/* Define a set of insns that requires a function unit.  This means that
   these insns produce their result after a delay and that there may be
   restrictions on the number of insns of this type that can be scheduled
   simultaneously.

   More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
   Each gives a set of operations and associated delays.  The first three
   operands must be the same for each operation for the same function unit.

   All delays are specified in cycles.

   1st operand: Name of function unit (mostly for documentation)
   2nd operand: Number of identical function units in CPU
   3rd operand: Total number of simultaneous insns that can execute on this
		function unit; 0 if unlimited.
   4th operand: Condition involving insn attribute, that, if true, specifies
		those insns that this expression applies to.
   5th operand: Constant delay after which insn result will be
		available.
   6th operand: Delay until next insn can be scheduled on the function unit
		executing this operation.  The meaning depends on whether or
		not the next operand is supplied.
   7th operand: If this operand is not specified, the 6th operand gives the
		number of cycles after the instruction matching the 4th
		operand begins using the function unit until a subsequent
		insn can begin.  A value of zero should be used for a
		unit with no issue constraints.  If only one operation can
		be executed a time and the unit is busy for the entire time,
		the 3rd operand should be specified as 1, the 6th operand
		should be specified as 0, and the 7th operand should not
		be specified.

		If this operand is specified, it is a list of attribute
		expressions.  If an insn for which any of these expressions
		is true is currently executing on the function unit, the
		issue delay will be given by the 6th operand.  Otherwise,
		the insn can be immediately scheduled (subject to the limit
		on the number of simultaneous operations executing on the
		unit.)  */
DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')

/* Define attribute computation for `asm' instructions.  */
DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )

/* Definition of a conditional execution meta operation.  Automatically
   generates new instances of DEFINE_INSN, selected by having attribute
   "predicable" true.  The new pattern will contain a COND_EXEC and the
   predicate at top-level.

   Operand:
   0: The predicate pattern.  The top-level form should match a
      relational operator.  Operands should have only one alternative.
   1: A C expression giving an additional condition for recognizing
      the generated pattern.
   2: A template or C code to produce assembler output.  */
DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')

/* SEQUENCE appears in the result of a `gen_...' function
   for a DEFINE_EXPAND that wants to make several insns.
   Its elements are the bodies of the insns that should be made.
   `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')

/* Refers to the address of its argument.  This is only used in alias.c.  */
DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')

/* ----------------------------------------------------------------------
   Expressions used for insn attributes.  These also do not appear in
   actual rtl code in the compiler.
   ---------------------------------------------------------------------- */

/* Definition of an insn attribute.
   1st operand: name of the attribute
   2nd operand: comma-separated list of possible attribute values
   3rd operand: expression for the default value of the attribute. */
DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')

/* Marker for the name of an attribute. */
DEF_RTL_EXPR(ATTR, "attr", "s", 'x')

/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
   in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
   pattern.

   (set_attr "name" "value") is equivalent to
   (set (attr "name") (const_string "value"))  */
DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')

/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
   specify that attribute values are to be assigned according to the
   alternative matched.

   The following three expressions are equivalent:

   (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
			    (eq_attrq "alternative" "2") (const_string "a2")]
			   (const_string "a3")))
   (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
				 (const_string "a3")])
   (set_attr "att" "a1,a2,a3")
 */
DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')

/* A conditional expression true if the value of the specified attribute of
   the current insn equals the specified value.  The first operand is the
   attribute name and the second is the comparison value.  */
DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')

/* A conditional expression which is true if the specified flag is
   true for the insn being scheduled in reorg.

   genattr.c defines the following flags which can be tested by
   (attr_flag "foo") expressions in eligible_for_delay.

   forward, backward, very_likely, likely, very_unlikely, and unlikely.  */

DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')

/* ----------------------------------------------------------------------
   Expression types used for things in the instruction chain.

   All formats must start with "iuu" to handle the chain.
   Each insn expression holds an rtl instruction and its semantics
   during back-end processing.
   See macros's in "rtl.h" for the meaning of each rtx->fld[].

   ---------------------------------------------------------------------- */

/* An instruction that cannot jump.  */
DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')

/* An instruction that can possibly jump.
   Fields ( rtx->fld[] ) have exact same meaning as INSN's.  */
DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')

/* An instruction that can possibly call a subroutine
   but which will not change which instruction comes next
   in the current function.
   Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
   All other fields ( rtx->fld[] ) have exact same meaning as INSN's.  */
DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')

/* A marker that indicates that control will not flow through.  */
DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')

/* Holds a label that is followed by instructions.
   Operand:
   3: is used in jump.c for the use-count of the label.
   4: is used in flow.c to point to the chain of label_ref's to this label.
   5: is a number that is unique in the entire compilation.
   6: is the user-given name of the label, if any.
   7: is the alternate label name.  */
DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuu00iss", 'x')
     
/* Say where in the code a source line starts, for symbol table's sake.
   Operand:
   3: filename, if line number > 0, note-specific data otherwise.
   4: line number if > 0, enum note_insn otherwise.
   5: unique number if line number == note_insn_deleted_label.  */
DEF_RTL_EXPR(NOTE, "note", "iuu0ni", 'x')

/* ----------------------------------------------------------------------
   Top level constituents of INSN, JUMP_INSN and CALL_INSN.
   ---------------------------------------------------------------------- */
   
/* Conditionally execute code.
   Operand 0 is the condition that if true, the code is executed.
   Operand 1 is the code to be executed (typically a SET). 

   Semantics are that there are no side effects if the condition
   is false.  This pattern is created automatically by the if_convert
   pass run after reload or by target-specific splitters.  */
DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')

/* Several operations to be done in parallel (perhaps under COND_EXEC).  */
DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')

/* A string that is passed through to the assembler as input.
     One can obviously pass comments through by using the
     assembler comment syntax.
     These occur in an insn all by themselves as the PATTERN.
     They also appear inside an ASM_OPERANDS
     as a convenient way to hold a string.  */
DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')

/* An assembler instruction with operands.
   1st operand is the instruction template.
   2nd operand is the constraint for the output.
   3rd operand is the number of the output this expression refers to.
     When an insn stores more than one value, a separate ASM_OPERANDS
     is made for each output; this integer distinguishes them.
   4th is a vector of values of input operands.
   5th is a vector of modes and constraints for the input operands.
     Each element is an ASM_INPUT containing a constraint string
     and whose mode indicates the mode of the input operand.
   6th is the name of the containing source file.
   7th is the source line number.  */
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')

/* A machine-specific operation.
   1st operand is a vector of operands being used by the operation so that
     any needed reloads can be done.
   2nd operand is a unique value saying which of a number of machine-specific
     operations is to be performed.
   (Note that the vector must be the first operand because of the way that
   genrecog.c record positions within an insn.)
   This can occur all by itself in a PATTERN, as a component of a PARALLEL,
   or inside an expression.  */
DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')

/* Similar, but a volatile operation and one which may trap.  */
DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')

/* Vector of addresses, stored as full words.  */
/* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')

/* Vector of address differences X0 - BASE, X1 - BASE, ...
   First operand is BASE; the vector contains the X's.
   The machine mode of this rtx says how much space to leave
   for each difference and is adjusted by branch shortening if
   CASE_VECTOR_SHORTEN_MODE is defined.
   The third and fourth operands store the target labels with the
   minimum and maximum addresses respectively.
   The fifth operand stores flags for use by branch shortening.
  Set at the start of shorten_branches:
   min_align: the minimum alignment for any of the target labels.
   base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
   min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
   max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
   min_after_base: true iff minimum address target label is after BASE.
   max_after_base: true iff maximum address target label is after BASE.
  Set by the actual branch shortening process:
   offset_unsigned: true iff offsets have to be treated as unsigned.
   scale: scaling that is necessary to make offsets fit into the mode.

   The third, fourth and fifth operands are only valid when
   CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
   compilations.  */
     
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')

/* ----------------------------------------------------------------------
   At the top level of an instruction (perhaps under PARALLEL).
   ---------------------------------------------------------------------- */

/* Assignment.
   Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
   Operand 2 is the value stored there.
   ALL assignment must use SET.
   Instructions that do multiple assignments must use multiple SET,
   under PARALLEL.  */
DEF_RTL_EXPR(SET, "set", "ee", 'x')

/* Indicate something is used in a way that we don't want to explain.
   For example, subroutine calls will use the register
   in which the static chain is passed.  */
DEF_RTL_EXPR(USE, "use", "e", 'x')

/* Indicate something is clobbered in a way that we don't want to explain.
   For example, subroutine calls will clobber some physical registers
   (the ones that are by convention not saved).  */
DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')

/* Call a subroutine.
   Operand 1 is the address to call.
   Operand 2 is the number of arguments.  */

DEF_RTL_EXPR(CALL, "call", "ee", 'x')

/* Return from a subroutine.  */

DEF_RTL_EXPR(RETURN, "return", "", 'x')

/* Conditional trap.
   Operand 1 is the condition.
   Operand 2 is the trap code.
   For an unconditional trap, make the condition (const_int 1).  */
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')

/* ----------------------------------------------------------------------
   Primitive values for use in expressions.
   ---------------------------------------------------------------------- */

/* numeric integer constant */
DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')

/* numeric floating point constant.
   Operand 0 ('e') is the MEM that stores this constant in memory, or
   various other things (see comments at immed_double_const in
   varasm.c).
   Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the
   current function.
   Remaining operands hold the actual value.  They are all 'w' and
   there may be from 1 to 4; see rtl.c.  */
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')

/* String constant.  Used only for attributes right now.  */
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')

/* This is used to encapsulate an expression whose value is constant
   (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
   recognized as a constant operand rather than by arithmetic instructions.  */

DEF_RTL_EXPR(CONST, "const", "e", 'o')

/* program counter.  Ordinary jumps are represented
   by a SET whose first operand is (PC).  */
DEF_RTL_EXPR(PC, "pc", "", 'o')

/* Used in the cselib routines to describe a value.  */
DEF_RTL_EXPR(VALUE, "value", "0", 'o')

/* A register.  The "operand" is the register number, accessed with
   the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
   than a hardware register is being referred to.  The second operand
   doesn't really exist.  Unfortunately, however, the compiler
   implicitly assumes that a REG can be transformed in place into a
   MEM, and therefore that a REG is at least as big as a MEM.  To
   avoid this memory overhead, which is likely to be substantial,
   search for uses of PUT_CODE that turn REGs into MEMs, and fix them
   somehow.  Then, the trailing `0' can be removed here.  */
DEF_RTL_EXPR(REG, "reg", "i0", 'o')

/* A scratch register.  This represents a register used only within a
   single insn.  It will be turned into a REG during register allocation
   or reload unless the constraint indicates that the register won't be
   needed, in which case it can remain a SCRATCH.  This code is
   marked as having one operand so it can be turned into a REG.  */
DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')

/* One word of a multi-word value.
   The first operand is the complete value; the second says which word.
   The WORDS_BIG_ENDIAN flag controls whether word number 0
   (as numbered in a SUBREG) is the most or least significant word.

   This is also used to refer to a value in a different machine mode.
   For example, it can be used to refer to a SImode value as if it were
   Qimode, or vice versa.  Then the word number is always 0.  */
DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')

/* This one-argument rtx is used for move instructions
   that are guaranteed to alter only the low part of a destination.
   Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
   has an unspecified effect on the high part of REG,
   but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
   is guaranteed to alter only the bits of REG that are in HImode.

   The actual instruction used is probably the same in both cases,
   but the register constraints may be tighter when STRICT_LOW_PART
   is in use.  */

DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')

/* (CONCAT a b) represents the virtual concatenation of a and b
   to make a value that has as many bits as a and b put together.
   This is used for complex values.  Normally it appears only
   in DECL_RTLs and during RTL generation, but not in the insn chain.  */
DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')

/* A memory location; operand is the address.  Can be nested inside a
   VOLATILE.  The second operand is the alias set to which this MEM
   belongs.  We use `0' instead of `w' for this field so that the
   field need not be specified in machine descriptions.  */
DEF_RTL_EXPR(MEM, "mem", "e0", 'o')

/* Reference to an assembler label in the code for this function.
   The operand is a CODE_LABEL found in the insn chain.
   The unprinted fields 1 and 2 are used in flow.c for the
   LABEL_NEXTREF and CONTAINING_INSN.  */
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')

/* Reference to a named label: the string that is the first operand,
   with `_' added implicitly in front.
   Exception: if the first character explicitly given is `*',
   to give it to the assembler, remove the `*' and do not add `_'.  */
DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')

/* The condition code register is represented, in our imagination,
   as a register holding a value that can be compared to zero.
   In fact, the machine has already compared them and recorded the
   results; but instructions that look at the condition code
   pretend to be looking at the entire value and comparing it.  */
DEF_RTL_EXPR(CC0, "cc0", "", 'o')

/* Reference to the address of a register.  Removed by purge_addressof after
   CSE has elided as many as possible.
   1st operand: the register we may need the address of.
   2nd operand: the original pseudo regno we were generated for.
   3rd operand: the decl for the object in the register, for
     put_reg_in_stack.  */

DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')

/* =====================================================================
   A QUEUED expression really points to a member of the queue of instructions
   to be output later for postincrement/postdecrement.
   QUEUED expressions never become part of instructions.
   When a QUEUED expression would be put into an instruction,
   instead either the incremented variable or a copy of its previous
   value is used.
   
   Operands are:
   0. the variable to be incremented (a REG rtx).
   1. the incrementing instruction, or 0 if it hasn't been output yet.
   2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
   3. the body to use for the incrementing instruction
   4. the next QUEUED expression in the queue.
   ====================================================================== */

DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')

/* ----------------------------------------------------------------------
   Expressions for operators in an rtl pattern
   ---------------------------------------------------------------------- */

/* if_then_else.  This is used in representing ordinary
   conditional jump instructions.
     Operand:
     0:  condition
     1:  then expr
     2:  else expr */
DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')

/* General conditional. The first operand is a vector composed of pairs of
   expressions.  The first element of each pair is evaluated, in turn.
   The value of the conditional is the second expression of the first pair
   whose first expression evaluates non-zero.  If none of the expressions is
   true, the second operand will be used as the value of the conditional.

   This should be replaced with use of IF_THEN_ELSE.  */
DEF_RTL_EXPR(COND, "cond", "Ee", 'x')

/* Comparison, produces a condition code result.  */
DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')

/* plus */
DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')

/* Operand 0 minus operand 1.  */
DEF_RTL_EXPR(MINUS, "minus", "ee", '2')

/* Minus operand 0.  */
DEF_RTL_EXPR(NEG, "neg", "e", '1')

DEF_RTL_EXPR(MULT, "mult", "ee", 'c')

/* Operand 0 divided by operand 1.  */
DEF_RTL_EXPR(DIV, "div", "ee", '2')
/* Remainder of operand 0 divided by operand 1.  */
DEF_RTL_EXPR(MOD, "mod", "ee", '2')

/* Unsigned divide and remainder.  */
DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
DEF_RTL_EXPR(UMOD, "umod", "ee", '2')

/* Bitwise operations.  */
DEF_RTL_EXPR(AND, "and", "ee", 'c')

DEF_RTL_EXPR(IOR, "ior", "ee", 'c')

DEF_RTL_EXPR(XOR, "xor", "ee", 'c')

DEF_RTL_EXPR(NOT, "not", "e", '1')

/* Operand:
     0:  value to be shifted.
     1:  number of bits.  */
DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */

/* Minimum and maximum values of two operands.  We need both signed and
   unsigned forms.  (We cannot use MIN for SMIN because it conflicts
   with a macro of the same name.) */

DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')

/* These unary operations are used to represent incrementation
   and decrementation as they occur in memory addresses.
   The amount of increment or decrement are not represented
   because they can be understood from the machine-mode of the
   containing MEM.  These operations exist in only two cases:
   1. pushes onto the stack.
   2. created automatically by the life_analysis pass in flow.c.  */
DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')

/* These binary operations are used to represent generic address
   side-effects in memory addresses, except for simple incrementation
   or decrementation which use the above operations.  They are
   created automatically by the life_analysis pass in flow.c.
   The first operand is a REG which is used as the address.
   The second operand is an expression that is assigned to the
   register, either before (PRE_MODIFY) or after (POST_MODIFY)
   evaluating the address.
   Currently, the compiler can only handle second operands of the
   form (plus (reg) (reg)) and (plus (reg) (const_int)), where
   the first operand of the PLUS has to be the same register as
   the first operand of the *_MODIFY.  */
DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')

/* Comparison operations.  The ordered comparisons exist in two
   flavors, signed and unsigned.  */
DEF_RTL_EXPR(NE, "ne", "ee", '<')
DEF_RTL_EXPR(EQ, "eq", "ee", '<')
DEF_RTL_EXPR(GE, "ge", "ee", '<')
DEF_RTL_EXPR(GT, "gt", "ee", '<')
DEF_RTL_EXPR(LE, "le", "ee", '<')
DEF_RTL_EXPR(LT, "lt", "ee", '<')
DEF_RTL_EXPR(GEU, "geu", "ee", '<')
DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
DEF_RTL_EXPR(LEU, "leu", "ee", '<')
DEF_RTL_EXPR(LTU, "ltu", "ee", '<')

/* Additional floating point unordered comparision flavors.  */
DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')

/* These are equivalent to unordered or ... */
DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')

/* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')

/* Represents the result of sign-extending the sole operand.
   The machine modes of the operand and of the SIGN_EXTEND expression
   determine how much sign-extension is going on.  */
DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')

/* Similar for zero-extension (such as unsigned short to int).  */
DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')

/* Similar but here the operand has a wider mode.  */
DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')

/* Similar for extending floating-point values (such as SFmode to DFmode).  */
DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')

/* Conversion of fixed point operand to floating point value.  */
DEF_RTL_EXPR(FLOAT, "float", "e", '1')

/* With fixed-point machine mode:
   Conversion of floating point operand to fixed point value.
   Value is defined only when the operand's value is an integer.
   With floating-point machine mode (and operand with same mode):
   Operand is rounded toward zero to produce an integer value
   represented in floating point.  */
DEF_RTL_EXPR(FIX, "fix", "e", '1')

/* Conversion of unsigned fixed point operand to floating point value.  */
DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')

/* With fixed-point machine mode:
   Conversion of floating point operand to *unsigned* fixed point value.
   Value is defined only when the operand's value is an integer.  */
DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')

/* Absolute value */
DEF_RTL_EXPR(ABS, "abs", "e", '1')

/* Square root */
DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')

/* Find first bit that is set.
   Value is 1 + number of trailing zeros in the arg.,
   or 0 if arg is 0.  */
DEF_RTL_EXPR(FFS, "ffs", "e", '1')

/* Reference to a signed bit-field of specified size and position.
   Operand 0 is the memory unit (usually SImode or QImode) which
   contains the field's first bit.  Operand 1 is the width, in bits.
   Operand 2 is the number of bits in the memory unit before the
   first bit of this field.
   If BITS_BIG_ENDIAN is defined, the first bit is the msb and
   operand 2 counts from the msb of the memory unit.
   Otherwise, the first bit is the lsb and operand 2 counts from
   the lsb of the memory unit.  */
DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')

/* Similar for unsigned bit-field.  */
DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')

/* For RISC machines.  These save memory when splitting insns.  */

/* HIGH are the high-order bits of a constant expression.  */
DEF_RTL_EXPR(HIGH, "high", "e", 'o')

/* LO_SUM is the sum of a register and the low-order bits
   of a constant expression.  */
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')

/* Header for range information.  Operand 0 is the NOTE_INSN_RANGE_BEG insn.
   Operand 1 is the NOTE_INSN_RANGE_END insn.  Operand 2 is a vector of all of
   the registers that can be substituted within this range.  Operand 3 is the
   number of calls in the range.  Operand 4 is the number of insns in the
   range.  Operand 5 is the unique range number for this range.  Operand 6 is
   the basic block # of the start of the live range.  Operand 7 is the basic
   block # of the end of the live range.  Operand 8 is the loop depth.  Operand
   9 is a bitmap of the registers live at the start of the range.  Operand 10
   is a bitmap of the registers live at the end of the range.  Operand 11 is
   marker number for the start of the range.  Operand 12 is the marker number
   for the end of the range.  */
DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')

/* Registers that can be substituted within the range.  Operand 0 is the
   original pseudo register number.  Operand 1 will be filled in with the
   pseudo register the value is copied for the duration of the range.  Operand
   2 is the number of references within the range to the register.  Operand 3
   is the number of sets or clobbers of the register in the range.  Operand 4
   is the number of deaths the register has.  Operand 5 is the copy flags that
   give the status of whether a copy is needed from the original register to
   the new register at the beginning of the range, or whether a copy from the
   new register back to the original at the end of the range.  Operand 6 is the
   live length.  Operand 7 is the number of calls that this register is live
   across.  Operand 8 is the symbol node of the variable if the register is a
   user variable.  Operand 9 is the block node that the variable is declared
   in if the register is a user variable. */
DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')

/* Information about a local variable's ranges.  Operand 0 is an EXPR_LIST of
   the different ranges a variable is in where it is copied to a different
   pseudo register.  Operand 1 is the block that the variable is declared in.
   Operand 2 is the number of distinct ranges.  */
DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')

/* Information about the registers that are live at the current point.  Operand
   0 is the live bitmap.  Operand 1 is the original block number.  */
DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')

/* A unary `__builtin_constant_p' expression.  These are only emitted
   during RTL generation, and then only if optimize > 0.  They are
   eliminated by the first CSE pass. */
DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')

/* A placeholder for a CALL_INSN which may be turned into a normal call,
   a sibling (tail) call or tail recursion.

   Immediately after RTL generation, this placeholder will be replaced
   by the insns to perform the call, sibcall or tail recursion.

   This RTX has 4 operands.  The first three are lists of instructions to
   perform the call as a normal call, sibling call and tail recursion
   respectively.  The latter two lists may be NULL, the first may never
   be NULL.

   The last operand is the tail recursion CODE_LABEL, which may be NULL if no 
   potential tail recursive calls were found.

   The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
   after we select a call method.

   This method of tail-call elimination is intended to be replaced by
   tree-based optimizations once front-end conversions are complete.  */
DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')

/* Describes a merge operation between two vector values.
   Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
   that specifies where the parts of the result are taken from.  Set bits
   indicate operand 0, clear bits indicate operand 1.  The parts are defined
   by the mode of the vectors.  */
DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')

/* Describes an operation that selects parts of a vector.
   Operands 0 is the source vector, operand 1 is a PARALLEL that contains
   a CONST_INT for each of the subparts of the result vector, giving the
   number of the source subpart that should be stored into it.  */
DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')

/* Describes a vector concat operation.  Operands 0 and 1 are the source
   vectors, the result is a vector that is as long as operands 0 and 1
   combined and is the concatenation of the two source vectors.  */
DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')

/* Describes a vector constant.  Each part of the PARALLEL that is operand 0
   describes a constant for one of the subparts.  */
DEF_RTL_EXPR(VEC_CONST, "vec_const", "e", 'x')

/* Describes an operation that converts a small vector into a larger one by
   duplicating the input values.  The output vector mode must have the same
   submodes as the input vector mode, and the number of output parts must be
   an integer multiple of the number of input parts.  */
DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
     
/* Addition with signed saturation */
DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')

/* Addition with unsigned saturation */
DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')

/* Operand 0 minus operand 1, with signed saturation.  */
DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')

/* Operand 0 minus operand 1, with unsigned saturation.  */
DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')

/* Signed saturating truncate.  */
DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')

/* Unsigned saturating truncate.  */
DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')

/* The SSA phi operator. 

   The argument is a vector of 2N rtxes.  Element 2N+1 is a CONST_INT
   containing the block number of the predecessor through which control
   has passed when the register at element 2N is used.

   Note that PHI may only appear at the beginning of a basic block.

   ??? There may be multiple PHI insns, but they are all evaluated
   in parallel.  This probably ought to be changed to use a real
   PARALLEL, as that would be less confusing and more in the spirit
   of canonical RTL.  It is, however, easier to manipulate this way.  */
DEF_RTL_EXPR(PHI, "phi", "E", 'x')


/*
Local variables:
mode:c
End:
*/