rtl.def (DEFINE_COND_EXEC): New.

	* rtl.def (DEFINE_COND_EXEC): New.
	* md.texi: Document it.

	* gensupport.c (input_file): Remove.
	(struct queue_elem): Add lineno.
	(rtx_ready_queue): Remove.
	(errors): New.
	(predicable_default): New.
	(predicable_true, predicable_false): New.
	(define_attr_queue, define_attr_tail): New.
	(define_insn_queue, define_insn_tail): New.
	(define_cond_exec_queue, define_cond_exec_tail): New.
	(other_queue, other_tail): New.
	(queue_pattern): New.
	(process_rtx): Add patterns to the appropriate queues.
	(is_predicable, identify_predicable_attribute): New.
	(n_alternatives, collect_insn_data): New.
	(alter_predicate_for_insn, alter_test_for_insn): New.
	(shift_output_template, alter_output_for_insn): New.
	(process_one_cond_exec, process_define_cond_exec): New.
	(init_md_reader): Read the entire file.  Process define_cond_exec.
	(read_md_rtx): Return elements from the queues.

From-SVN: r33751

gcc/ChangeLog

 2000-05-06  Richard Henderson  <rth@cygnus.com>
 
+	* rtl.def (DEFINE_COND_EXEC): New.
+	* md.texi: Document it.
+
+	* gensupport.c (input_file): Remove.
+	(struct queue_elem): Add lineno.
+	(rtx_ready_queue): Remove.
+	(errors): New.
+	(predicable_default): New.
+	(predicable_true, predicable_false): New.
+	(define_attr_queue, define_attr_tail): New.
+	(define_insn_queue, define_insn_tail): New.
+	(define_cond_exec_queue, define_cond_exec_tail): New.
+	(other_queue, other_tail): New.
+	(queue_pattern): New.
+	(process_rtx): Add patterns to the appropriate queues.
+	(is_predicable, identify_predicable_attribute): New.
+	(n_alternatives, collect_insn_data): New.
+	(alter_predicate_for_insn, alter_test_for_insn): New.
+	(shift_output_template, alter_output_for_insn): New.
+	(process_one_cond_exec, process_define_cond_exec): New.
+	(init_md_reader): Read the entire file.  Process define_cond_exec.
+	(read_md_rtx): Return elements from the queues.
+
+2000-05-06  Richard Henderson  <rth@cygnus.com>
+
 	* flow.c (mark_set_1): Don't update conditional life info
 	if the register is not_dead.
 

gcc/md.texi

@@ -37,6 +37,8 @@ See the next chapter for information on the C header file.
 * Insn Splitting::      Splitting Instructions into Multiple Instructions.
 * Peephole Definitions::Defining machine-specific peephole optimizations.
 * Insn Attributes::     Specifying the value of attributes for generated insns.
+* Conditional Execution::Generating @code{define_insn} patterns for
+                           predication.
 @end menu
 
 @node Patterns
@@ -4558,3 +4560,83 @@ used during their execution and there is no way of representing that
 conflict.  We welcome any examples of how function unit conflicts work
 in such processors and suggestions for their representation.
 @end ifset
+
+@node Conditional Execution
+@section Conditional Execution
+@cindex conditional execution
+@cindex predication
+
+A number of architectures provide for some form of conditional
+execution, or predication.  The hallmark of this feature is the
+ability to nullify most of the instructions in the instruction set.
+When the instruction set is large and not entirely symmetric, it
+can be quite tedious to describe these forms directly in the
+@file{.md} file.  An alternative is the @code{define_cond_exec} template.
+
+@findex define_cond_exec
+@smallexample
+(define_cond_exec
+  [@var{predicate-pattern}]
+  "@var{condition}"
+  "@var{output template}")
+@end smallexample
+
+@var{predicate-pattern} is the condition that must be true for the
+insn to be executed at runtime and should match a relational operator.
+One can use @code{match_operator} to match several relational operators
+at once.  Any @code{match_operand} operands must have no more than one
+alternative.
+
+@var{condition} is a C expression that must be true for the generated
+pattern to match.
+
+@findex current_insn_predicate
+@var{output template} is a string similar to the @code{define_insn}
+output template (@pxref{Output Template}), except that the @samp{*}
+and @samp{@@} special cases do not apply.  This is only useful if the
+assembly text for the predicate is a simple prefix to the main insn.
+In order to handle the general case, there is a global variable
+@code{current_insn_predicate} that will contain the entire predicate
+if the current insn is predicated, and will otherwise be @code{NULL}.
+
+When @code{define_cond_exec} is used, an implicit reference to 
+the @code{predicable} instruction attribute is made. 
+@xref{Insn Attributes}.  This attribute must be boolean (i.e. have
+exactly two elements in its @var{list-of-values}).  Further, it must
+not be used with complex expressions.  That is, the default and all
+uses in the insns must be a simple constant, not dependant on the 
+alternative or anything else.
+
+For each @code{define_insn} for which the @code{predicable} 
+attribute is true, a new @code{define_insn} pattern will be
+generated that matches a predicated version of the instruction.
+For example,
+
+@smallexample
+(define_insn "addsi"
+  [(set (match_operand:SI 0 "register_operand" "r")
+        (plus:SI (match_operand:SI 1 "register_operand" "r")
+                 (match_operand:SI 2 "register_operand" "r")))]
+  "@var{test1}"
+  "add %2,%1,%0")
+
+(define_cond_exec
+  [(ne (match_operand:CC 0 "register_operand" "c")
+       (const_int 0))]
+  "@var{test2}"
+  "(%0)")
+@end smallexample
+
+@noindent
+generates a new pattern
+
+@smallexample
+(define_insn ""
+  [(cond_exec
+     (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
+     (set (match_operand:SI 0 "register_operand" "r")
+          (plus:SI (match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r"))))]
+  "(@var{test2}) && (@var{test1})"
+  "(%3) add %2,%1,%0")
+@end smallexample

gcc/rtl.def

@@ -310,6 +310,19 @@ DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
 /* Define attribute computation for `asm' instructions.  */
 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
 
+/* Definition of a conditional execution meta operation.  Automatically
+   generates new instances of DEFINE_INSN, selected by having attribute
+   "predicable" true.  The new pattern will contain a COND_EXEC and the
+   predicate at top-level.
+
+   Operand:
+   0: The predicate pattern.  The top-level form should match a
+      relational operator.  Operands should have only one alternative.
+   1: A C expression giving an additional condition for recognizing
+      the generated pattern.
+   2: A template or C code to produce assembler output.  */
+DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
+
 /* SEQUENCE appears in the result of a `gen_...' function
    for a DEFINE_EXPAND that wants to make several insns.
    Its elements are the bodies of the insns that should be made.