Add new tests to backends and architecture;
Merge commit "Add regression test for Yosys PR 896"

backends
=======
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419

simple
=========
+ 1. passes/techmap/attrmap.cc
There is example in help block create example with
(* keep="true" *) attribute and run example

+ 2. passes/techmap/dff2dffe.cc
execute with  -unmap parameter

+ 3. passes/techmap/dff2dffs.cc

+ 4. passes/techmap/extract.cc
Lot of variations of input parameters is not excersised

? 5. passes/techmap/extract_counter.cc
This is specific to greenpak4 architecture, but idea is to have counter
in design and call this after synth_greenpak

+ 6. passes/techmap/shregmap.cc.
This also seams to be greenpak4 specific, but extracting shift register

misc
========
1. passes/techmap/insbuf.cc

Testing problems:
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419
2.dff2dffe -direct - skipped: ERROR: Found error in internal cell
\dffe.$procdff$47 ($dffe) at
3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal
cell

1. Add tests for synth_anlogic command
Now this tests are commented because of:
+ iverilog -o testbench ../testbench.v synth.v ../../common.v
../../../../../techlibs/common/simcells.v
../../../../../techlibs/anlogic/cells_sim.v
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind
wire/reg/memory `A' in `testbench.uut._09_'
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to
elaborate r-value: (INIT)>>(A)
2 error(s) during elaboration.

2. Add 'regression' test

Signed-off-by: Clifford Wolf <clifford@clifford.at>