Testing problems:
frontends.read_liberty_error.read_liberty_error_read_liberty_redefenition_of_module
- Typo in the message "Re-definition of of cell/module..."

IV frontends
=============

For frontends idea is that you do not do read_verilog but some you are
reading input in different format.
Since most of formats yosys can also read and write you can use plain
verilog write blif for example
and use that as source for this coverage. For liberty files many
examples can be found so that is also in list of tasks

1.
http://scratch.clifford.at/coverage_html/frontends/blif/blifparse.cc.gcov.html
2.
http://scratch.clifford.at/coverage_html/frontends/ilang/ilang_frontend.cc.gcov.html
3.
http://scratch.clifford.at/coverage_html/frontends/json/jsonparse.cc.gcov.html
4.
http://scratch.clifford.at/coverage_html/frontends/liberty/liberty.cc.gcov.html