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yosys-tests
Unverified Commit f76690a5 by Miodrag Milanović Committed by GitHub
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Merge pull request #11 from SergeyDegtyar/master 

Add new tests to 'regression' test group
parents 8d7699bf 92201d14
Showing with 2414 additions and 8 deletions
misc/Makefile
......@@ -30,6 +30,7 @@ $(eval $(call template,torder,torder torder_stop torder_noautostop ))
#trace
$(eval $(call template,trace,trace ))
$(eval $(call template,trace_mem,trace_mem ))
#write_file
$(eval $(call template,write_file,write_file write_file_a ))
......@@ -43,6 +44,9 @@ $(eval $(call template,show, show show_colorattr show_colors show_color show_enu
#scc
$(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
#scatter
$(eval $(call template,scatter, scatter ))
......@@ -140,4 +144,11 @@ $(eval $(call template,sat, sat_dump_cnf sat_dump_json sat_dump_vcd sat_initstep
$(eval $(call template,sim,sim sim_a sim_clock sim_d sim_n sim_rstlen sim_vcd sim_w sim_zinit ))
$(eval $(call template,sim_mem,sim sim_a sim_clockn sim_clock_mem sim_d sim_n sim_resetn sim_reset sim_rstlen sim_vcd sim_w sim_zinit_mem ))
#splitnets
$(eval $(call template,splitnets, splitnets splitnets_format splitnets_ports splitnets_driver splitnets_dpf ))
$(eval $(call template,splitnets_logic, splitnets splitnets_format splitnets_ports splitnets_driver splitnets_dpf ))
#splice
$(eval $(call template,splice, splice splice_sel_by_cell splice_sel_by_wire splice_sel_any_bit splice_wires splice_no_outputs splice_port splice_no_port ))
.PHONY: all clean
misc/scc_feedback/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o_mid,o_rtl;
always @(posedge cin)
A <= o_mid;
assign o_mid = x & o_rtl;
assign o_rtl = y & o_mid;
endmodule
misc/scc_hier_feedback/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o_mid,o_rtl;
always @(posedge cin)
A <= o_mid;
middle u_mid (.x(x),.y(o_rtl),.o(o_mid));
u_rtl inst_u_rtl (.x(o_mid),.y(y),.o(o_rtl));
endmodule
module middle
(
input x,
input y,
output o
);
wire o1,o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
module u_rtl
(
input x,
input y,
output o
);
wire o1,o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
misc/scripts/rename_wire.ys
read_verilog ../top.v
proc
tee -o result.log rename -wire middle mid_module
tee -o result.log rename -wire o mid_o
misc/scripts/scc.ys
read_verilog ../top.v
proc
tee -o result.log scc top
synth
tee -o result.log scc top
misc/scripts/splice.ys 0 → 100644
read_verilog ../top.v
tee -o result.log splice
proc
tee -o result.log splice
synth
tee -o result.log splice
misc/scripts/splice_no_outputs.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -no_outputs
misc/scripts/splice_no_port.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -no_port q_b
misc/scripts/splice_port.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -port q_b
misc/scripts/splice_sel_any_bit.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -sel_any_bit
misc/scripts/splice_sel_by_cell.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -sel_by_cell
misc/scripts/splice_sel_by_wire.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -sel_by_wire
misc/scripts/splice_wires.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -wires
misc/scripts/splitnets.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets
misc/scripts/splitnets_dpf.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -driver -ports -format www
misc/scripts/splitnets_driver.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -driver
misc/scripts/splitnets_format.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -format ()
misc/scripts/splitnets_ports.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -ports
misc/scripts/trace.ys
read_verilog ../top.v
tee -o result.log trace synth -top top
proc
tee -o result.log trace synth -top top
synth
tee -o result.log trace synth -top top
misc/scripts/trace_mem.ys 0 → 100644
read_verilog ../top.v
tee -o result.log trace synth -top top
proc
memory
tee -o result.log trace synth -top top
synth
tee -o result.log trace synth -top top
misc/splice/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/splitnets/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/splitnets_logic/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/trace_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
regression/Makefile
......@@ -20,4 +20,99 @@ endef
#case_stmt_assertion
$(eval $(call template,case_stmt_assertion,case_stmt_assertion))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
#issue_00041
$(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078 What should be in top.v?
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
$(eval $(call template,issue_00081,issue_00081))
#issue_00082
#yosys> read_verilog top_fault.v
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
#$(eval $(call template,issue_00082,issue_00082))
#issue_00083
#Warning: Deep recursion in AST simplifier.
#Does this design contain insanely long expressions?
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
#$(eval $(call template,issue_00083,issue_00083))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
#issue_00085
$(eval $(call template,issue_00085,issue_00085))
#issue_00086
$(eval $(call template,issue_00086,issue_00086))
#issue_00088
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top.v' to AST representation.
#top.v:6: ERROR: syntax error, unexpected $undefined
#$(eval $(call template,issue_00089,issue_00089))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
# correct behavior
#../top.v:1: syntax error
#../top.v:1: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00093,issue_00093))
#issue_00095
#../top.v:1: syntax error
#../top.v:1: error: Invalid variable list in port declaration.
#../top.v:1: error: duplicate declaration for net or variable 'c' in 'a'.
#$(eval $(call template,issue_00095,issue_00095))
#issue_00096
#../top.v:2: syntax error
#../top.v:1: error: syntax error in integer variable list.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00096,issue_00096))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
.PHONY: all clean
regression/issue_00018/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00018/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
regression/issue_00041/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00041/top.v 0 → 100644
module top(b);
input b;
task DoSomething(input [7:0] A);
endtask
endmodule
regression/issue_00059/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00059/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00065/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00065/top.v 0 → 100644
module top(
alu_data_d_in,
alu_data_d_out
);
input [7:0]alu_data_d_in;
output[7:0]alu_data_d_out;
wire [7:0]swap_out;
genvar i;
generate
for ( i = 7 ; ( i >= 4 ) ; i = ( i - 1 ) )
begin : swap_h
assign swap_out[i] = alu_data_d_in[( ( i - 4 ) )];
end
endgenerate
generate
//for ( i = 0 ; ( i <4 ) ; i = ( i + 1 ) ) //OK
for ( i = 3 ; ( i >=0 ) ; i = ( i - 1 ) ) //FAIL
begin : swap_l
assign swap_out[i] = alu_data_d_in[(i+4 )];
end
endgenerate
assign alu_data_d_out = swap_out;
endmodule
regression/issue_00067/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00067/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00067/top_fault.v 0 → 100644
module top(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00071/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00071/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00071/top_fault.v 0 → 100644
module top(b);
input b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00078/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00078/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00078/top_fault.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00081/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00081/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00081/top_fault.v 0 → 100644
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00082/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00082/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00082/top_fault.v 0 → 100644
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00083/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00083/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00083/top_fault.v 0 → 100644
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00084/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [9:0] addr = 0;
reg ce = 0;
wire [7:0] q;
top uut (
.clk(clk),
.addr(addr),
.ce(ce),
.q(q)
);
always @(posedge clk) begin
addr <= addr + 1;
end
always @(posedge clk) begin
#3;
ce <= !ce;
end
uut_mem_checker q_test(.clk(clk), .en(ce), .A(q));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'b00000000)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00084/top.v 0 → 100644
module top (addr, ce, q, clk);
input clk;
input [9:0] addr;
input ce;
output reg [7:0] q;
reg [7:0] ram[1023:0];
always @(posedge clk)
begin
if (ce)
begin
q <= ram[addr];
end
end
endmodule
regression/issue_00085/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00085/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00085/top_fault.v 0 → 100644
module a;assign a = 0'sh0;
endmodule
regression/issue_00086/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00086/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00086/top_fault.v 0 → 100644
module top(b);
input b;
reg N=0.0/0'H0;
endmodule
regression/issue_00088/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00088/top.v 0 → 100644
parameter X = 2;
module top(b);
input b;
parameter Y = 3;
endmodule
regression/issue_00089/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00089/top.v 0 → 100644
module top(A, clk, rst);
input clk, rst;
output A;
always @(posedge clk, posedge rst) begin
A <= '0';
end; // << like this
endmodule
regression/issue_00091/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00091/top.v 0 → 100644
module top(A, clk, rst);
input clk, rst;
output A;
parameter GPIO_COUNT = 16;
initial begin
if (GPIO_COUNT < 0 || GPIO_COUNT > 16) begin
$display("Parameter Error: GPIO_COUNT must be in range 0..16");
$finish;
end
end
endmodule
regression/issue_00093/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00093/top.v 0 → 100644
module top(b);inout b;reg c;assign+0-c=b;endmodule
regression/issue_00095/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00095/top.v 0 → 100644
module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule
regression/issue_00096/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00096/top.v 0 → 100644
module top(b);integer
inout b;reg c;assign&0=0;assign 0=0;always
i=0;always
if(8)b=_;always
if(8)b=M&0;endmodule
regression/issue_00098/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
always @(clk)
a <= a + 1;
top uut (
.a (a),
.z (z)
);
assert_Z check_output(clk,z[0]);
endmodule
regression/issue_00098/top.v 0 → 100644
module top(a,z);
input [7:0] a;
output [7:0] z;
parameter pos = 1;
assign z = ff(a);
function [7:0] ff;
parameter pos2 = pos + 1;
input [7:0] arg1;
begin
ff = arg1[pos2:0];
end
endfunction
endmodule
regression/issue_00099/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
wire o1,o2,o3;
always @(clk)
a <= a + 1;
top uut (
.in (a),
.out (z),
.out1 (o1),
.out2 (o2),
.out3 (o3)
);
assert_Z check_output1(clk,o1);
assert_Z check_output2(clk,o2);
assert_Z check_output3(clk,o3);
endmodule
regression/issue_00099/top.v 0 → 100644
module top(in, out, out1, out2, out3);
input [7:0] in;
output [7:0] out;
output out1;
output out2;
output out3;
parameter p = 23;
function [7:0] test1;
input [7:0] i;
parameter p = 42;
begin
test1 = i + p;
end
endfunction
function [7:0] test2;
input [7:0] i;
parameter p2 = p+42;
begin
test2 = i + p2;
end
endfunction
function [7:0] test3;
input [7:0] i;
begin
test3 = i + p;
end
endfunction
assign out1 = test1(in);
assign out2 = test2(in);
assign out3 = test3(in);
endmodule
regression/issue_00102/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [35:0] b;
top uut (
.a (clk),
.b (b)
);
assert_Z check_output1(clk,b[0]);
endmodule
regression/issue_00102/top.v 0 → 100644
module top (
a, b
);
input a;
output [35:0] b;
reg [35:0] G;
reg F;
reg H;
reg I;
reg J;
reg [5:0] K;
reg [9:0] L;
reg [9:0] M;
assign b = muxer(G, {L , H , F , M, J , I}, K, 24, 0);
function [35:0] muxer;
input [35:0] vector;
input [23:0] slice;
input [5:0] index;
input size;
integer size;
input offset;
integer offset;
integer i;
reg [35:0] muxed_value;
begin
muxed_value = vector;
for (i = 0; i < 24; i = i+1)
muxed_value[index * size + offset + i] = slice[i];
muxer = muxed_value;
end
endfunction
endmodule
regression/issue_00111/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [127:0] state,key = 0;
wire [127:0] out;
/*always @(posedge clk)
begin
state = state + 2300;
key = key + 2500;
end
top uut (
.state (state ),
.key (key ),
.out (out )
);*/
/*genvar index;
generate
for (index=0; index < 128; index=index+25)
begin: gen_code_label
assert_Z check_output(clk,out[index]);
end
endgenerate*/
assert_Z check_output(clk,out[0]);
endmodule
regression/issue_00111/top.v 0 → 100644
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module top(state, key, out);
input [127:0] state, key;
output [127:0] out;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
always @ (*)
begin
s0 <= state ^ key;
k0 <= key;
end
expand_key_128
a1 (k0, k1, k0b, 8'h1),
a2 (k1, k2, k1b, 8'h2),
a3 (k2, k3, k2b, 8'h4),
a4 (k3, k4, k3b, 8'h8),
a5 (k4, k5, k4b, 8'h10),
a6 (k5, k6, k5b, 8'h20),
a7 (k6, k7, k6b, 8'h40),
a8 (k7, k8, k7b, 8'h80),
a9 (k8, k9, k8b, 8'h1b),
a10 (k9, , k9b, 8'h36);
one_round
r1 (s0, k0b, s1),
r2 (s1, k1b, s2),
r3 (s2, k2b, s3),
r4 (s3, k3b, s4),
r5 (s4, k4b, s5),
r6 (s5, k5b, s6),
r7 (s6, k6b, s7),
r8 (s7, k7b, s8),
r9 (s8, k8b, s9);
final_round
rf (s9, k9b, out);
endmodule
module expand_key_128(in, out_1, out_2, rcon);
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (*)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 ({k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (*)
out_1 <= {k0b, k1b, k2b, k3b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* one AES round for every two clock cycles */
module one_round (state_in, key, state_out);
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (s0, p00, p01, p02, p03),
t1 (s1, p10, p11, p12, p13),
t2 (s2, p20, p21, p22, p23),
t3 (s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (*)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (state_in, key_in, state_out);
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (s0, {p00, p01, p02, p03}),
S4_2 (s1, {p10, p11, p12, p13}),
S4_3 (s2, {p20, p21, p22, p23}),
S4_4 (s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (*)
state_out <= {z0, z1, z2, z3};
endmodule
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module table_lookup (state, p0, p1, p2, p3);
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (b0, {p0[23:0], p0[31:24]}),
t1 ( b1, {p1[15:0], p1[31:16]}),
t2 (b2, {p2[7:0], p2[31:8]} ),
t3 (b3, p3);
endmodule
/* substitue four bytes in a word */
module S4 (in, out);
input [31:0] in;
output [31:0] out;
S
S_0 (in[31:24], out[31:24]),
S_1 (in[23:16], out[23:16]),
S_2 (in[15:8], out[15:8] ),
S_3 (in[7:0], out[7:0] );
endmodule
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (in, out);
input [7:0] in;
output [31:0] out;
S
s0 (in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
/* S box */
module S (in, out);
input [7:0] in;
output reg [7:0] out;
always @ (*)
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS (in, out);
input [7:0] in;
output reg [7:0] out;
always @ (*)
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
regression/run.sh
......@@ -12,12 +12,12 @@ mkdir $1/work_$2
cd $1/work_$2
if [ "$2" = "verify" ]; then
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
else
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v)
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v) ../../../../../techlibs/xilinx/brams_bb.v
fi
if [ "$2" = "falsify" ]; then
......
regression/scripts/issue_00018.ys 0 → 100644
read_verilog ../top.v
synth -top top
select -assert-any w:*i
write_verilog synth.v
regression/scripts/issue_00041.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00059.ys 0 → 100644
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
write_verilog synth.v
regression/scripts/issue_00065.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00067.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00071.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00078.ys 0 → 100644
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog synth.v
regression/scripts/issue_00081.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00082.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00083.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00084.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -top top
write_verilog synth.v
regression/scripts/issue_00085.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00086.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00088.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00089.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00091.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00093.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00095.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00096.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00098.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00099.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00102.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00111.ys 0 → 100644
read_verilog ../top.v
synth -top top
splitnets -ports
hierarchy -check
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/Makefile
......@@ -38,8 +38,8 @@ $(eval $(call template,tristate_const_1, tristate))
$(eval $(call template,tristate_const_data, tristate))
# Demoting I/O port
$(eval $(call template,inout_port, tristate))
$(eval $(call template,inout_port_demote, tristate))
$(eval $(call template,inout_port, deminout deminout_synth))
$(eval $(call template,inout_port_demote, deminout deminout_synth))
# MACC cells
$(eval $(call template,macc, macc))
......@@ -88,11 +88,14 @@ $(eval $(call template,attrmap,attrmap attrmap_modattr))
#dff2dffe -unmap
# dff2dffe_unmap_direct - skipped: ERROR: Found error in internal cell \dffe.$procdff$47 ($dffe) at
$(eval $(call template,dff2dffe_unmap,dff2dffe_unmap dff2dffe_unmap_mince))
$(eval $(call template,dff2dffe_unmap,dff2dffe_unmap dff2dffe_unmap_mince dff2dffe_unmap_direct))
#dff2dffs
$(eval $(call template,dff2dffs,dff2dffs))
#dffsr2dff
$(eval $(call template,dffsr2dff,dffsr2dff))
#extract
$(eval $(call template,extract,extract_cell_attr extract_compat extract_constports extract_map_design extract_ignore_parameters extract_ignore_param extract_map extract_mine_cells_span extract_mine_limit_matches_per_module extract_mine_max_fanout extract_mine_min_freq extract_mine_split extract_mine extract_nodefaultswaps extract_perm extract_swap extract_verbose extract_wire_attr ))
......@@ -118,5 +121,8 @@ $(eval $(call template,flowmap,flowmap flowmap_cells flowmap_debug_relax flowmap
$(eval $(call template,flowmap_latch,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
$(eval $(call template,flowmap_mem,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
#iopadmap
$(eval $(call template,iopadmap,iopadmap))
.PHONY: all clean
simple/dffsr2dff/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule
simple/dffsr2dff/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
`ifndef BUG
.clr (1'b1),
.pre (1'b1),
`else
.clr (1'b0),
.pre (1'b0),
`endif
.d (a ),
.q (b )
);
endmodule
simple/iopadmap/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
simple/iopadmap/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
reg [1:0] io_buf;
assign io = io_buf;
`ifndef BUG
always @(en or i)
io_buf[0] <= (en)? i : 1'bZ;
always @(en or i)
io_buf[1] <= (i)? en : 1'bZ;
assign o = (en)? io : 2'bZZ;
`else
always @(en or i)
io_buf[0] <= (en)? ~i : 1'bZ;
always @(en or i)
io_buf[1] <= (i)? ~en : 1'bZ;
assign o = (en)? ~io : 2'bZZ;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple/scripts/deminout.ys 0 → 100644
read_verilog ../top.v
deminout
write_verilog synth.v
simple/scripts/deminout_synth.ys 0 → 100644
read_verilog ../top.v
synth -top top
deminout
write_verilog synth.v
simple/scripts/dff2dffe_unmap_direct.ys
read_verilog ../top.v
proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
synth -top top
dff2dffe -direct $dff $dffe
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
flatten
opt
......
simple/scripts/dffsr2dff.ys 0 → 100644
read_verilog ../top.v
proc
dffsr2dff
techmap
dffsr2dff
design -reset
read_verilog ../top.v
synth -top top
dffsr2dff
flatten
opt
opt_rmdff
dffsr2dff
write_verilog synth.v
simple/scripts/iopadmap.ys 0 → 100644
read_verilog ../top.v
proc
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
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