correct always_latch syntax

bc6412d1 · Miodrag Milanovic · 64ab84a7 · bc6412d1
Commit bc6412d1 authored Nov 30, 2019 by Miodrag Milanovic
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frontends/verilog_lexer/top_always.v
+3 -3

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--- a/frontends/verilog_lexer/top_always.v
+++ b/frontends/verilog_lexer/top_always.v
@@ -4,10 +4,10 @@ module mux2 (S,A,B,Y,Y1);
    output reg Y,Y1;

    always_ff @(*)
-		Y = (S)? B : A;
+		  Y = (S)? B : A;

-    always_latch @(*)
-		Y1 = (~S)? B : A;
+    always_latch
+		  Y1 = (~S)? B : A;

 endmodule