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yosys-tests
Commit bc6412d1 by Miodrag Milanovic
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correct always_latch syntax

parent 64ab84a7
Showing with 3 additions and 3 deletions
frontends/verilog_lexer/top_always.v
...@@ -4,10 +4,10 @@ module mux2 (S,A,B,Y,Y1); ...@@ -4,10 +4,10 @@ module mux2 (S,A,B,Y,Y1);
output reg Y,Y1; output reg Y,Y1;
always_ff @(*) always_ff @(*)
Y = (S)? B : A; Y = (S)? B : A;
always_latch @(*) always_latch
Y1 = (~S)? B : A; Y1 = (~S)? B : A;
endmodule endmodule
......
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