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yosys-tests
Commit abd361f8 by Miodrag Milanovic
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Fix eol

parent d323bec2
Showing with 2 additions and 4 deletions
backends/write_verilog/top_lhs.v
...@@ -3,4 +3,4 @@ wire [1:2] b; ...@@ -3,4 +3,4 @@ wire [1:2] b;
wire [3:1] c; wire [3:1] c;
wire f; wire f;
assign {b, f} = c; assign {b, f} = c;
endmodule endmodule
\ No newline at end of file
backends/write_verilog/write_verilog_simple_lhs.pat
assign b = c\[3:2\]; assign b = c\[3:2\];
\ No newline at end of file
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