Fix eol

abd361f8 · Miodrag Milanovic · d323bec2 · abd361f8 · abd361f8
Commit abd361f8 authored Nov 25, 2020 by Miodrag Milanovic
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backends/write_verilog/top_lhs.v
+1 -2

backends/write_verilog/write_verilog_simple_lhs.pat
+1 -2

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--- a/backends/write_verilog/top_lhs.v
+++ b/backends/write_verilog/top_lhs.v
@@ -3,4 +3,4 @@ wire [1:2] b;
 wire [3:1] c;
 wire f;
 assign {b, f} = c;
-endmodule
\ No newline at end of file
+endmodule
--- a/backends/write_verilog/write_verilog_simple_lhs.pat
+++ b/backends/write_verilog/write_verilog_simple_lhs.pat
-assign b = c\[3:2\];
\ No newline at end of file
+assign b = c\[3:2\];