remove unnecessary rerun inside tests

simple_reviewed/expose/expose_evert_dff_shared.ys

@@ -7,7 +7,3 @@ flatten
 opt
 opt_rmdff
 expose -evert-dff
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/expose/expose_input.ys

@@ -6,7 +6,3 @@ flatten
 opt
 opt_rmdff
 expose -input
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/extract/extract_cell_attr.ys

 read_verilog ../top.v
 extract -map ../top.v -cell_attr attr
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_compat.ys

 read_verilog ../top.v
 extract -map ../top.v -compat $dff a
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_constports.ys

 read_verilog ../top.v
 extract -map ../top.v -constports
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_ignore_param.ys

 read_verilog ../top.v
 extract -map ../top.v -ignore_param $dff param
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_ignore_parameters.ys

 read_verilog ../top.v
 extract -map ../top.v  -ignore_parameters
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_map.ys

 read_verilog ../top.v
 extract -map ../top.v
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_map_design.ys

 read_verilog ../top.v
 design -save top_test
 extract -map %top_test
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_nodefaultswaps.ys

 read_verilog ../top.v
 extract  -map ../top.v -nodefaultswaps
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_perm.ys

 read_verilog ../top.v
 extract  -map ../top.v -perm $dff D,CLK D,CLK
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_swap.ys

 read_verilog ../top.v
 extract  -map ../top.v -swap $dff D,CLK
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_verbose.ys

 read_verilog ../top.v
 extract  -map ../top.v -verbose
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract/extract_wire_attr.ys

 read_verilog ../top.v
 extract  -map ../top.v -wire_attr attr
-design -reset
-read_verilog ../top.v
-proc
-

simple_reviewed/extract_counter/extract_counter.ys

 read_verilog ../top.v
 synth_greenpak4
 extract_counter
-design -reset
-read_verilog ../top.v
-

simple_reviewed/extract_counter/extract_counter_down.ys

 read_verilog ../top_down.v
 synth_greenpak4
 extract_counter
-design -reset
-read_verilog ../top.v
-

simple_reviewed/extract_counter/extract_counter_maxwidth.ys

 read_verilog ../top.v
 synth_greenpak4
 extract_counter -maxwidth 4
-design -reset
-read_verilog ../top.v
-

simple_reviewed/extract_counter/extract_counter_pout.ys

 read_verilog ../top.v
 synth_greenpak4
 extract_counter -pout X
-design -reset
-read_verilog ../top.v
-

simple_reviewed/extract_counter/extract_counter_pout_without_args_fail.ys

 read_verilog ../top_err.v
 synth_greenpak4
 extract_counter -pout
-design -reset
-read_verilog ../top_err.v
-

simple_reviewed/hierarchy/hierarchy_huge.ys

 read_verilog ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/SimDTM.v
 proc
 hierarchy -generate -check -simcheck -purge_lib -keep_positionals -keep_portwidths -nokeep_asserts -auto-top
-design -reset
-read_verilog ../top.v
-synth
-

simple_reviewed/memory/memory_bram_cant_open_rules_file_fail.ys

 read_verilog ../top.v
 proc
 memory_bram -rules uuu
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_bram_opt.ys

 read_verilog ../top.v
 proc
 memory -bram ../words.v
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_bram_syntax_error_in_rules_fail.ys

 read_verilog ../top.v
 proc
 memory_bram -rules ../rules.v
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_memx_opt.ys

 read_verilog ../top.v
 proc
 memory -memx
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_nomap.ys

@@ -2,8 +2,3 @@ read_verilog ../top.v
 proc
 memory -nomap
 memory_map
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_nordff.ys

@@ -15,8 +15,3 @@ memory_nordff
 memory_map
 memory_nordff
 memory_unpack
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_nordff_opt.ys

 read_verilog ../top.v
 proc
 memory -nordff
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_nordff_single_port.ys

@@ -15,4 +15,3 @@ memory_nordff
 memory_map
 memory_nordff
 memory_unpack
-

simple_reviewed/memory/memory_share.ys

@@ -16,8 +16,3 @@ memory_map
 memory_share
 memory
 memory_share
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/memory/memory_single_port.ys

 read_verilog ../top_single_port.v
 proc
 memory
-
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/opt_lut/opt_lut_dlogic.ys

 read_verilog ../top.v
 synth_ice40
 opt_lut -dlogic $_ANDNOT_:A=I0
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/opt_lut/opt_lut_limit.ys

 read_verilog ../top.v
 synth_ice40
 opt_lut -limit 2
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/opt_lut/opt_lut_limit_0.ys

 read_verilog ../top.v
 synth_ice40
 opt_lut -limit 0
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/shregmap/shregmap_clkpol_any.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -clkpol any
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_clkpol_neg.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -clkpol neg
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_clkpol_pos.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -clkpol pos
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_enpol_any.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -enpol any
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_enpol_any_or_none.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -enpol any_or_none
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_enpol_neg.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -enpol neg
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_enpol_none.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -enpol none
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_enpol_pos.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -enpol pos
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_init.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -init
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_keep_after.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -keep_after 5
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_keep_before.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -keep_before 3
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_match.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -match \GP_DFF
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_match_clkpol_fail.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -match -clkpol any
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_match_enpol_fail.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -match foobar -enpol any
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_match_params_fail.ys

 read_verilog ../top.v
 shregmap -params -match 2:2
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_maxlen.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -maxlen 10
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_minlen.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -minlen 4
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_params.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -params
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_resetable.ys

 read_verilog ../top_resetable.v
 synth_greenpak4
 shregmap
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_tech.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_zinit.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -zinit
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/shregmap_zinit_init_fail.ys

 read_verilog ../top.v
 synth_greenpak4 -run begin:map_luts
 shregmap -tech greenpak4 -zinit -init
-design -reset
-read_verilog ../top.v
-

simple_reviewed/shregmap/simplemap.ys

-read_verilog ../top.v
-prep
-simplemap
-synth
-

simple_reviewed/shregmap/simplemap_slice_concat.ys

-read_verilog ../top.v
-synth
-splice
-simplemap top
-synth
-

simple_reviewed/shregmap/simplemap_top.ys

-read_verilog ../top.v
-prep
-dff2dffe
-simplemap top
-synth
-

simple_reviewed/submod/submod_mem.ys

@@ -2,7 +2,3 @@ read_verilog ../top_mem.v
 memory_memx
 proc
 submod
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_generate_ice40_dsp.ys

 read_verilog ../top.v
 proc
 test_pmgen -generate ice40_dsp
-design -reset
-read_verilog ../top.v
-synth -top top
 

simple_reviewed/test_pmgen/test_pmgen_generate_peepopt_muldiv.ys

 read_verilog ../top.v
 proc
 test_pmgen -generate peepopt-muldiv
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_generate_peepopt_shiftmul.ys

 read_verilog ../top.v
 proc
 test_pmgen -generate peepopt-shiftmul
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_generate_reduce.ys

 read_verilog ../top.v
 proc
 test_pmgen -generate reduce
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_generate_xilinx_srl_fixed.ys

 read_verilog ../top.v
 proc
 test_pmgen -generate xilinx_srl.fixed
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_generate_xilinx_srl_variable.ys

 read_verilog ../top.v
 proc
 test_pmgen -generate xilinx_srl.variable
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_reduce_chain.ys

 read_verilog ../top.v
 proc
 test_pmgen -reduce_chain
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/test_pmgen/test_pmgen_reduce_tree.ys

 read_verilog ../top.v
 proc
 test_pmgen -reduce_tree
-design -reset
-read_verilog ../top.v
-synth -top top
-

simple_reviewed/wreduce/wreduce.ys

 read_verilog ../top.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_div.ys

 read_verilog ../top_div.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_keepdc.ys

 read_verilog ../top.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_keepdc_div.ys

 read_verilog ../top_div.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_keepdc_mem.ys

 read_verilog ../top_mem.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_keepdc_mul.ys

 read_verilog ../top_mul.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_keepdc_reduce.ys

 read_verilog ../top_reduce.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_mem.ys

 read_verilog ../top_mem.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce; clean; opt
-design -reset
-read_verilog ../top_mem.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_mem_synth.ys

+read_verilog ../top_mem.v
+synth -top top

simple_reviewed/wreduce/wreduce_memx.ys

 read_verilog ../top.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_div.ys

 read_verilog ../top_div.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_keepdc.ys

 read_verilog ../top.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_keepdc_div.ys

 read_verilog ../top_div.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_keepdc_mem.ys

 read_verilog ../top_mem.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_keepdc_mul.ys

 read_verilog ../top_mul.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_keepdc_reduce.ys

 read_verilog ../top_reduce.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_mem.ys

 read_verilog ../top_mem.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_mul.ys

 read_verilog ../top_mul.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_memx_reduce.ys

 read_verilog ../top_reduce.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_mul.ys

 read_verilog ../top_mul.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v

simple_reviewed/wreduce/wreduce_reduce.ys

 read_verilog ../top_reduce.v
 hierarchy -top top
 proc; opt; memory; dff2dffe; wreduce; clean; opt
-design -reset
-read_verilog ../top.v
-synth -top top
-write_verilog -noexpr -norename synth.v