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yosys-tests
Commit f200dc81 by SergeyDegtyar
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Remove unnecessary output files generation

parent 9c8c9592
Showing with 112 additions and 120 deletions
simple_reviewed/alu/gates.ys
read_verilog ../top.v
synth -top top
abc -g gates
stat
select -assert-count 98 t:$_ANDNOT_
select -assert-count 465 t:$_AND_
select -assert-count 32 t:$_DFF_P_
......
simple_reviewed/alu/luts.ys
read_verilog ../top.v
synth -top top
abc -lut 4
stat
select -assert-count 32 t:$_DFF_P_
select -assert-count 689 t:$lut
simple_reviewed/design_import/design_import.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
design -save top
design -import top
write_verilog synth.v
simple_reviewed/design_import/design_import_as.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
design -save top
design -import top -as top_new
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap.ys
......@@ -2,11 +2,11 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
tee -o result.log dump
dump
synth -top top
dff2dffe
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct.ys
......@@ -3,11 +3,11 @@ proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
tee -o result.log dump
dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct_match.ys
......@@ -6,4 +6,4 @@ dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_mince.ys
......@@ -2,11 +2,11 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
tee -o result.log dump
dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dffsr2dff/dffsr2dff.ys
......@@ -11,4 +11,4 @@ flatten
opt
opt_rmdff
dffsr2dff
write_verilog synth.v
simple_reviewed/expose/expose_cut.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -cut
write_verilog synth.v
simple_reviewed/expose/expose_dff.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dff.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dffr.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_evert.ys
......@@ -8,4 +8,4 @@ flatten
opt
opt_rmdff
expose -evert
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff.ys
......@@ -8,4 +8,4 @@ flatten
opt
opt_rmdff
expose -evert-dff
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff_shared.ys
......@@ -10,4 +10,4 @@ expose -evert-dff
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/expose/expose_evert_shared.ys
......@@ -6,4 +6,4 @@ opt
opt_rmdff
expose -evert -shared
expose -shared -evert
write_verilog synth.v
simple_reviewed/expose/expose_input.ys
......@@ -9,4 +9,4 @@ expose -input
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/expose/expose_sep.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -sep |
write_verilog synth.v
simple_reviewed/expose/expose_shared.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -shared
write_verilog synth.v
simple_reviewed/extract/extract_cell_attr.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -cell_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_compat.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -compat $dff a
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_constports.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -constports
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_param.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -ignore_param $dff param
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_parameters.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -ignore_parameters
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map_design.ys
......@@ -4,4 +4,4 @@ extract -map %top_test
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_mine.ys
read_verilog ../top.v
extract -mine out.ilang
write_verilog synth.v
simple_reviewed/extract/extract_mine_cells_span.ys
read_verilog ../top.v
extract -mine out.ilang -mine_cells_span 3 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_limit_matches_per_module.ys
read_verilog ../top.v
extract -mine out.ilang -mine_limit_matches_per_module 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_max_fanout.ys
read_verilog ../top.v
extract -mine out.ilang -mine_max_fanout 2
write_verilog synth.v
simple_reviewed/extract/extract_mine_min_freq.ys
read_verilog ../top.v
extract -mine out.ilang -mine_min_freq 10
write_verilog synth.v
simple_reviewed/extract/extract_mine_split.ys
read_verilog ../top.v
extract -mine out.ilang -mine_split 2 2
write_verilog synth.v
simple_reviewed/extract/extract_nodefaultswaps.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -nodefaultswaps
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_perm.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -perm $dff D,CLK D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_swap.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -swap $dff D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_verbose.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -verbose
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_wire_attr.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -wire_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_down.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_maxwidth.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter -maxwidth 4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter -pout X
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout_without_args_fail.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter -pout
design -reset
read_verilog ../top_err.v
write_verilog synth.v
simple_reviewed/flowmap/flowmap.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
synth -top top
flowmap
select -assert-any t:$lut
write_verilog synth.v
simple_reviewed/flowmap/flowmap_cells.ys
read_verilog ../top.v
synth -top top
flowmap -cells $dff top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_debug.ys
read_verilog ../top.v
synth -top top
flowmap -debug top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_debug_relax.ys
read_verilog ../top.v
synth -top top
flowmap -debug-relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_ffs.ys
read_verilog ../top_ffs.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_latch.ys
read_verilog ../top_latch.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_maxlut.ys
read_verilog ../top.v
synth -top top
flowmap -maxlut 4 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_minlut.ys
read_verilog ../top.v
synth -top top
flowmap -minlut 2 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_optarea.ys
read_verilog ../top.v
synth -top top
flowmap -optarea 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_alpha.ys
read_verilog ../top.v
synth -top top
flowmap -r-alpha 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_beta.ys
read_verilog ../top.v
synth -top top
flowmap -r-beta 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_gamma.ys
read_verilog ../top.v
synth -top top
flowmap -r-gamma 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax.ys
read_verilog ../top.v
synth -top top
flowmap -relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax_debug.ys
read_verilog ../top.v
synth -top top
flowmap -relax -debug top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax_debug_relax.ys
read_verilog ../top.v
synth -top top
flowmap -relax -debug-relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_top.ys
read_verilog ../top.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command.ys
read_verilog ../top.v
proc
fsm
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command_expand.ys
read_verilog ../top.v
proc
fsm -expand
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command_export.ys
read_verilog ../top.v
proc
fsm -export
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encfile.ys
read_verilog ../top.v
proc
fsm -encfile fsm.fsm
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_auto.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding auto
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_binary.ys
read_verilog ../top.v
proc
fsm -encoding binary
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_none.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding none
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_one-hot.ys
read_verilog ../top.v
proc
fsm -encoding one-hot
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_unknown.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding unknown
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_user.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding user
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_fm_set_fsm_file.ys
read_verilog ../top.v
proc
fsm -fm_set_fsm_file file.file
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_fullexpand.ys
read_verilog ../top.v
proc
fsm -fullexpand
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_nodetect.ys
read_verilog ../top.v
proc
fsm -nodetect
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_nomap.ys
read_verilog ../top.v
proc
fsm -nomap
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_norecode.ys
read_verilog ../top.v
proc
fsm -norecode
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_export/fsm_export_couldnt_open_file_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_all_opt.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_cant_open_encfile_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_cant_open_fm_set_fsm_file_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encfile.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_binary.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_binary_twice.ys
......@@ -8,4 +8,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_isnt_supported_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_one_hot.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_fm_set_fsm_file.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy.ys
......@@ -6,4 +6,4 @@ opt
hierarchy
synth -top top
hierarchy
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_auto_top.ys
read_verilog ../top.v
hierarchy -auto-top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_check.ys
read_verilog ../top.v
hierarchy -check -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_chparam.ys
read_verilog ../top.v
hierarchy -chparam x 1 -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_chparam_overwr.ys
read_verilog ../top.v
hierarchy -chparam x 1 -chparam x 2 -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_generate.ys
read_verilog ../top.v
hierarchy -generate dff adff adffn i@1:i o@2:o io@3:io
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_huge.ys
......@@ -4,4 +4,4 @@ hierarchy -generate -check -simcheck -purge_lib -keep_positionals -keep_portwidt
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_keep_portwidths.ys
read_verilog ../top.v
hierarchy -keep_portwidths -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_keep_positionals.ys
read_verilog ../top.v
hierarchy -keep_positionals -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_libdir.ys
read_verilog ../top.v
hierarchy -libdir libdir -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_module_not_found_fail.ys
read_verilog ../top.v
hierarchy -top uu
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_no_top_module_fail.ys
hierarchy -simcheck
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_nokeep_asserts.ys
read_verilog ../top.v
hierarchy -nokeep_asserts -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_purge_lib.ys
read_verilog ../top.v
hierarchy -purge_lib -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_simcheck.ys
read_verilog ../top.v
hierarchy -simcheck -top top
synth -top top
write_verilog synth.v
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