Merge pull request #86 from YosysHQ/eddie/fixes

Fix a number of tests (mainly in backend)

backends/write_aiger/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_aiger/write_aiger.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger_B.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -B result.out
 design -reset

backends/write_aiger/write_aiger_I.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -I aiger.aiger
 design -reset

backends/write_aiger/write_aiger_O.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -O aiger.aiger
 design -reset

backends/write_aiger/write_aiger__add_sub.ys

 read_verilog -sv ../../common/add_sub.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__adffs.ys → backends/write_aiger/write_aiger__adffs_fail.ys

 read_verilog -sv ../../common/adffs.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__counter.ys → backends/write_aiger/write_aiger__counter_fail.ys

 read_verilog -sv ../../common/counter.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__dffs.ys

 read_verilog -sv ../../common/dffs.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__latches.ys → backends/write_aiger/write_aiger__latches_fail.ys

 read_verilog -sv ../../common/latches.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__logic.ys

 read_verilog -sv ../../common/logic.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__mux.ys → backends/write_aiger/write_aiger__mux_fail.ys

 read_verilog -sv ../../common/mux.v
+proc
+techmap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger__tribuf.ys → backends/write_aiger/write_aiger__tribuf_fail.ys

 read_verilog -sv ../../common/tribuf.v
+proc
+simplemap
 aigmap
 write_aiger result.out
 design -reset

backends/write_aiger/write_aiger_ascii.ys

 read_verilog -sv ../top3.v
+proc
 aigmap
+simplemap
 write_aiger -ascii result.out
 design -reset
 read_aiger result.out

backends/write_aiger/write_aiger_ascii_diff_cells.ys

 read_verilog -sv ../top_diff_cells.v
+proc
+simplemap
 aigmap
 write_aiger -ascii aiger.aiger

backends/write_aiger/write_aiger_cant_open_file_fail.ys

-read_verilog -sv ../top_x_z.v
+read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -map tt/tt.map aiger.aiger

backends/write_aiger/write_aiger_diff_cells.ys

 read_verilog -sv ../top_diff_cells.v
+proc
+simplemap
 aigmap
 write_aiger aiger.aiger

backends/write_aiger/write_aiger_diff_cells_proc.ys

 read_verilog -sv ../top_diff_cells.v
-synth
+proc
+simplemap
 aigmap
 write_aiger aiger.aiger

backends/write_aiger/write_aiger_map.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -map a.map aiger.aiger
 design -reset

backends/write_aiger/write_aiger_mem_fail.ys

+read_verilog -sv ../top_mem.v
+proc
+simplemap
+aigmap
+write_aiger result.out

backends/write_aiger/write_aiger_miter.ys

 read_verilog -sv ../top3.v
-synth -top top
+proc
+simplemap
 aigmap
 write_aiger -miter result.out
 design -reset

backends/write_aiger/write_aiger_miter_and_asserts_fail.ys → backends/write_aiger/write_aiger_miter_and_asserts.ys

-read_verilog -sv ../top_x_z.v
+read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -miter aiger.aiger

backends/write_aiger/write_aiger_symbols.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -symbols result.out
 design -reset

backends/write_aiger/write_aiger_symbols_diff_cells.ys

 read_verilog -sv ../top_diff_cells.v
+proc
+simplemap
 aigmap
 write_aiger -symbols aiger.aiger

backends/write_aiger/write_aiger_unsupported_cell_type_fail.ys

 read_verilog -sv ../top_x_z.v
+proc
+simplemap
 synth
 write_aiger aiger.aiger

backends/write_aiger/write_aiger_vmap.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -vmap a.map aiger.aiger
 design -reset

backends/write_aiger/write_aiger_zinit.ys

 read_verilog -sv ../top3.v
+proc
+simplemap
 aigmap
 write_aiger -zinit aiger.aiger
 design -reset

backends/write_blif/top.v

@@ -5,6 +5,7 @@ module top
  input cin,
 
  output reg A,
+ output B,
  output reg cout
  );
 
@@ -31,11 +32,11 @@ always @(*) begin
         cout <=  cout1&cin~|y;
 end
 
-bb ubb (cin,y,x,A);
+bb ubb (cin,y,x,B);
 
 endmodule
 
-(* black_box *) module bb(in1, in2, clk, out1);
+(* blackbox *) module bb(in1, in2, clk, out1);
  input in1;
  input in2;
  input clk;

backends/write_verilog/top_logic.v

@@ -5,6 +5,7 @@ module top
  input cin,
 
  output reg A,
+ output B,
  output reg cout
  );
 
@@ -32,7 +33,7 @@ always @(*) begin
         cout <=  cout1&cin~|y;
 end
 
-bb ubb (cin,y,x,A);
+bb ubb (cin,y,x,B);
 
 endmodule
 

backends/write_xaiger/write_xaiger.ys

 read_verilog -sv ../top.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__add_sub.ys

 read_verilog -sv ../../common/add_sub.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__adffs.ys

 read_verilog -sv ../../common/adffs.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__counter.ys

 read_verilog -sv ../../common/counter.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__dffs.ys

 read_verilog -sv ../../common/dffs.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__latches.ys

 read_verilog -sv ../../common/latches.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__logic.ys

 read_verilog -sv ../../common/logic.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__mux.ys

 read_verilog -sv ../../common/mux.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger__tribuf.ys

 read_verilog -sv ../../common/tribuf.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger_ascii.ys

 read_verilog -sv ../top.v
+proc
+simplemap
 aigmap
 write_xaiger -ascii result.out

backends/write_xaiger/write_xaiger_cant_open_file_fail.ys

 read_verilog -sv ../top.v
+proc
+simplemap
 aigmap
 write_xaiger -map tt/tt.map xaiger.xaiger

backends/write_xaiger/write_xaiger_fsm.ys

 read_verilog -sv ../top_fsm.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger_fulladder.ys

 read_verilog -sv ../top_fulladder.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger_map.ys

 read_verilog -sv ../top.v
 proc
+simplemap
 aigmap
 write_xaiger -map a.map result.out

backends/write_xaiger/write_xaiger_mem.ys → backends/write_xaiger/write_xaiger_mem_fail.ys

 read_verilog -sv ../top_mem.v
+proc
+simplemap
 aigmap
 write_xaiger result.out

backends/write_xaiger/write_xaiger_vmap.pat

-aig 17 17 0 10 0
-2
-10
-16
-18
-20
-22
-24
-26
-28
-30

backends/write_xaiger/write_xaiger_vmap.ys

-read_verilog -sv ../top.v
-aigmap
-write_xaiger -vmap a.map result.out

misc/abc9/abc9_markgroups.ys

-read_verilog ../top.v
-proc
-dff2dffe
-synth -top top
-abc9 -markgroups -lut 2

regression/issue_01002/issue_01002.pat

-Estimated number of LCs:         75
+Estimated number of LCs:         86