Unverified Commit 1f84d9af by Miodrag Milanović Committed by GitHub

Merge pull request #86 from YosysHQ/eddie/fixes

Fix a number of tests (mainly in backend)
parents ae57d068 80832fa7
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -B result.out
design -reset
......
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -I aiger.aiger
design -reset
......
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -O aiger.aiger
design -reset
......
read_verilog -sv ../../common/add_sub.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/adffs.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/counter.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/dffs.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/latches.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/logic.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/mux.v
proc
techmap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../../common/tribuf.v
proc
simplemap
aigmap
write_aiger result.out
design -reset
......
read_verilog -sv ../top3.v
proc
aigmap
simplemap
write_aiger -ascii result.out
design -reset
read_aiger result.out
read_verilog -sv ../top_diff_cells.v
proc
simplemap
aigmap
write_aiger -ascii aiger.aiger
read_verilog -sv ../top_x_z.v
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -map tt/tt.map aiger.aiger
read_verilog -sv ../top_diff_cells.v
proc
simplemap
aigmap
write_aiger aiger.aiger
read_verilog -sv ../top_diff_cells.v
synth
proc
simplemap
aigmap
write_aiger aiger.aiger
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -map a.map aiger.aiger
design -reset
......
read_verilog -sv ../top_mem.v
proc
simplemap
aigmap
write_aiger result.out
read_verilog -sv ../top3.v
synth -top top
proc
simplemap
aigmap
write_aiger -miter result.out
design -reset
......
read_verilog -sv ../top_x_z.v
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -miter aiger.aiger
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -symbols result.out
design -reset
......
read_verilog -sv ../top_diff_cells.v
proc
simplemap
aigmap
write_aiger -symbols aiger.aiger
read_verilog -sv ../top_x_z.v
proc
simplemap
synth
write_aiger aiger.aiger
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -vmap a.map aiger.aiger
design -reset
......
read_verilog -sv ../top3.v
proc
simplemap
aigmap
write_aiger -zinit aiger.aiger
design -reset
......
......@@ -5,6 +5,7 @@ module top
input cin,
output reg A,
output B,
output reg cout
);
......@@ -31,11 +32,11 @@ always @(*) begin
cout <= cout1&cin~|y;
end
bb ubb (cin,y,x,A);
bb ubb (cin,y,x,B);
endmodule
(* black_box *) module bb(in1, in2, clk, out1);
(* blackbox *) module bb(in1, in2, clk, out1);
input in1;
input in2;
input clk;
......
......@@ -5,6 +5,7 @@ module top
input cin,
output reg A,
output B,
output reg cout
);
......@@ -32,7 +33,7 @@ always @(*) begin
cout <= cout1&cin~|y;
end
bb ubb (cin,y,x,A);
bb ubb (cin,y,x,B);
endmodule
......
read_verilog -sv ../top.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/add_sub.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/adffs.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/counter.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/dffs.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/latches.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/logic.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/mux.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../../common/tribuf.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../top.v
proc
simplemap
aigmap
write_xaiger -ascii result.out
read_verilog -sv ../top.v
proc
simplemap
aigmap
write_xaiger -map tt/tt.map xaiger.xaiger
read_verilog -sv ../top_fsm.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../top_fulladder.v
proc
simplemap
aigmap
write_xaiger result.out
read_verilog -sv ../top.v
proc
simplemap
aigmap
write_xaiger -map a.map result.out
aig 17 17 0 10 0
2
10
16
18
20
22
24
26
28
30
read_verilog -sv ../top.v
aigmap
write_xaiger -vmap a.map result.out
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -markgroups -lut 2
Estimated number of LCs: 75
Estimated number of LCs: 86
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