Skip to content

Y
yosys-tests
Commit ae57d068 by Miodrag Milanovic
Options

fix

parent 6c70ba2e
Showing with 2 additions and 2 deletions
regression/issue_00160/issue_00160.ys
read_verilog ../top.v
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
#equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment