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yosys-tests
Commit 08feab0a by Miodrag Milanovic
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fix arch tests

parent e630e78b
Showing with 28 additions and 16 deletions
architecture/synth_coolrunner2/synth_coolrunner2.ys
......@@ -8,11 +8,13 @@ proc
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
select -assert-count 1 t:MACROCELL_XOR
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR %% t:* %D
design -load read
hierarchy -top dffe
......@@ -22,8 +24,8 @@ proc
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
stat
select -assert-count 3 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
......
architecture/synth_coolrunner2/synth_coolrunner2_noflatten.ys
......@@ -9,10 +9,12 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
select -assert-count 1 t:MACROCELL_XOR
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR %% t:* %D
design -load read
hierarchy -top dffe
......@@ -23,7 +25,7 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 3 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
......
architecture/synth_coolrunner2/synth_coolrunner2_retime.ys
......@@ -9,10 +9,12 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
select -assert-count 1 t:MACROCELL_XOR
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR %% t:* %D
design -load read
hierarchy -top dffe
......@@ -23,7 +25,7 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 3 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
......
architecture/synth_coolrunner2/synth_coolrunner2_run.ys
......@@ -9,10 +9,12 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
select -assert-count 1 t:MACROCELL_XOR
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR %% t:* %D
design -load read
hierarchy -top dffe
......@@ -23,7 +25,7 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 3 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
......
architecture/synth_coolrunner2/synth_coolrunner2_top.ys
......@@ -9,10 +9,12 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
select -assert-count 1 t:MACROCELL_XOR
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR %% t:* %D
design -load read
hierarchy -top dffe
......@@ -23,7 +25,7 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 3 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
......
architecture/synth_coolrunner2/synth_coolrunner2_vout.ys
......@@ -9,10 +9,12 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
select -assert-count 1 t:MACROCELL_XOR
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR %% t:* %D
design -load read
hierarchy -top dffe
......@@ -23,7 +25,7 @@ equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 3 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
......
architecture/synth_ice40/synth_ice40_nobram.ys
......@@ -33,5 +33,5 @@ cd top
stat
select -assert-count 6 t:SB_DFF
select -assert-count 384 t:SB_DFFE
select -assert-count 372 t:SB_LUT4
select -assert-count 373 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D
architecture/synth_intel/synth_intel_nobram.ys
......@@ -35,5 +35,5 @@ synth_intel -nobram
#design -load postopt
cd top
select -assert-count 520 t:dffeas
select -assert-count 976 t:fiftyfivenm_lcell_comb
select -assert-count 977 t:fiftyfivenm_lcell_comb
select -assert-none t:dffeas t:fiftyfivenm_lcell_comb %% t:* %D
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