Commits · bc1329a72bf6cfcfd5289468d770232635a25c7c · lvzhengyang / sv2v · GitLab

02 May, 2022 1 commit
- defer elaboration of void functions · 9eceb556
  Zachary Snow committed 2 years ago
  
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16 Jul, 2021 1 commit
- remove some dead code · dd951740
  Zachary Snow committed 3 years ago
  
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23 Apr, 2019 2 commits
- conversions are applied per-file · 33dc4b3f
```
- NestTF refactored to cover all package items
- fixed issue where type traverse skipped typedefs
```
  Zachary Snow committed 5 years ago
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- random documentation and cleanup · c8894ceb
  Zachary Snow committed 5 years ago
  
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22 Mar, 2019 1 commit
- revamped support system with most SystemVerilog types and signed types · cecd141e
  Zachary Snow committed 5 years ago
  
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08 Mar, 2019 2 commits
- pivoted to general Verilog-2005 targeting · d7f641b8
  Zachary Snow committed 6 years ago
  
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- some fixes for 'VTR' targetted conversions · 9f0857d6
  Zachary Snow committed 6 years ago
  
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07 Mar, 2019 1 commit
- functions and typedefs can now appear at the top level · 0f4a60be
  Zachary Snow committed 6 years ago
  
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06 Mar, 2019 1 commit
- function return type logic to implicit conversion · 4c49bd11
  Zachary Snow committed 6 years ago
  
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