Commits · 9a38225b1de25f3d2998dc2ff3f2e8fa1494a8b8 · lvzhengyang / sv2v · GitLab

02 Apr, 2019 1 commit
- add support for specifying compile-time defines · f59ed11e
  Zachary Snow committed 5 years ago
  
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28 Mar, 2019 1 commit
- updated CLI to support include dirs and multiple files · 0d9ed3e1
  Zachary Snow committed 5 years ago
  
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18 Mar, 2019 1 commit
- completely rewrote preprocessor; more extensive directive support (include, timescale) · acfbdb07
  Zachary Snow committed 5 years ago
  
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08 Mar, 2019 1 commit
- pivoted to general Verilog-2005 targeting · d7f641b8
  Zachary Snow committed 6 years ago
  
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28 Feb, 2019 2 commits
- cleaned up command line args module a bit · 945923b3
  Zachary Snow committed 6 years ago
  
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- directory re-org; streamline build setup · 7bc81ef6
  Zachary Snow committed 6 years ago
  
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26 Feb, 2019 1 commit
- split up Yosys and VTR targeting · cf232677
  Zachary Snow committed 6 years ago
  
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18 Feb, 2019 1 commit
- added logic to module items; toying with initial Conversion · d47c5493
  Zachary Snow committed 6 years ago
  
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10 Feb, 2019 1 commit
- support for reduction ops, non-named/non-identifier module instantiation arguments, always @* · 14ba5dae
  Zachary Snow committed 6 years ago
  
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09 Feb, 2019 1 commit
- hacky, preliminary support for port declarations in module header · ebd7ae67
  Zachary Snow committed 6 years ago
  
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08 Feb, 2019 2 commits
- Basic build setup! · 8bd58e96
  Zachary Snow committed 6 years ago
  
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- Refactor project setup for our purposes · b46009af
  Zachary Snow committed 6 years ago
  
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