Refactor project setup for our purposes

Language/SystemVerilog.hs

+-- | A parser for SystemVerilog.
+module Language.SystemVerilog
+  ( module Language.SystemVerilog.AST
+  , module Language.SystemVerilog.Parser
+  ) where
+
+import Language.SystemVerilog.AST
+import Language.SystemVerilog.Parser
+

Language/Verilog/AST.hs → Language/SystemVerilog/AST.hs

-module Language.Verilog.AST
+module Language.SystemVerilog.AST
   ( Identifier
   , Module     (..)
   , ModuleItem (..)

Language/Verilog/Parser.hs → Language/SystemVerilog/Parser.hs

-module Language.Verilog.Parser
+module Language.SystemVerilog.Parser
   ( parseFile
   , preprocess
   ) where
 
-import Language.Verilog.AST
-import Language.Verilog.Parser.Lex
-import Language.Verilog.Parser.Parse
-import Language.Verilog.Parser.Preprocess
-import Language.Verilog.Parser.Tokens
+import Language.SystemVerilog.AST
+import Language.SystemVerilog.Parser.Lex
+import Language.SystemVerilog.Parser.Parse
+import Language.SystemVerilog.Parser.Preprocess
+import Language.SystemVerilog.Parser.Tokens
 
 -- | Parses a file given a table of predefined macros, the file name, and the file contents.
 parseFile :: [(String, String)] -> FilePath -> String -> [Module]

Language/Verilog/Parser/Lex.x → Language/SystemVerilog/Parser/Lex.x

 {
 {-# OPTIONS_GHC -w #-}
-module Language.Verilog.Parser.Lex
+module Language.SystemVerilog.Parser.Lex
   ( alexScanTokens
   ) where
 
-import Language.Verilog.Parser.Tokens
+import Language.SystemVerilog.Parser.Tokens
 
 }
 

Language/Verilog/Parser/Parse.y → Language/SystemVerilog/Parser/Parse.y

 {
-module Language.Verilog.Parser.Parse (modules) where
+module Language.SystemVerilog.Parser.Parse (modules) where
 
 import Data.Bits
 import Data.List
 
 import Data.BitVec
-import Language.Verilog.AST
-import Language.Verilog.Parser.Tokens
+import Language.SystemVerilog.AST
+import Language.SystemVerilog.Parser.Tokens
 }
 
 %name modules

Language/Verilog/Parser/Preprocess.hs → Language/SystemVerilog/Parser/Preprocess.hs

-module Language.Verilog.Parser.Preprocess
+module Language.SystemVerilog.Parser.Preprocess
   ( uncomment
   , preprocess
   ) where

Language/Verilog/Parser/Tokens.hs → Language/SystemVerilog/Parser/Tokens.hs

-module Language.Verilog.Parser.Tokens
+module Language.SystemVerilog.Parser.Tokens
   ( Token     (..)
   , TokenName (..)
   , Position  (..)

Language/Verilog/Simulator.hs → Language/SystemVerilog/Simulator.hs

-module Language.Verilog.Simulator
+module Language.SystemVerilog.Simulator
   ( Simulator
   , SimCommand  (..)
   , SimResponse (..)
@@ -16,7 +16,7 @@ import Data.VCD hiding (Var, step)
 import qualified Data.VCD as VCD
 
 import Data.BitVec
-import Language.Verilog.Netlist
+import Language.SystemVerilog.Netlist
 
 --check msg = putStrLn msg >> hFlush stdout
 

Language/Verilog.hs

--- | A parser for Verilog.
-module Language.Verilog
-  ( module Language.Verilog.AST
-  , module Language.Verilog.Parser
-  ) where
-
-import Language.Verilog.AST
-import Language.Verilog.Parser
-

sv2v.cabal

+name:    sv2v
+version: 0.0.1
+
+category: Language, Hardware, Embedded
+
+synopsis: SystemVerilog to Verilog conversion
+
+description:
+  A tool for coverting SystemVerilog to Verilog. Also exposes a limited
+  SystemVerilog parser and AST. Forked from the Verilog parser found at
+  https://github.com/tomahawkins/verilog
+
+author:     Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>
+maintainer: Zachary Snow <zach@zachjs.com>
+
+license:      BSD3
+license-file: LICENSE
+
+homepage: https://github.com/zachjs/sv2v
+
+build-type:    Simple
+cabal-version: >= 1.10
+
+library
+  default-language: Haskell2010
+  build-tools:
+    alex  >= 3 && < 4,
+    happy >= 1 && < 2
+  build-depends:
+    base       >= 4.8.2.0   && < 5.0,
+    array      >= 0.5.1.0   && < 0.6
+
+  exposed-modules:
+    Data.BitVec
+    Language.SystemVerilog
+    Language.SystemVerilog.AST
+    Language.SystemVerilog.Parser
+    Language.SystemVerilog.Parser.Lex
+    Language.SystemVerilog.Parser.Parse
+    Language.SystemVerilog.Parser.Preprocess
+    Language.SystemVerilog.Parser.Tokens
+
+  ghc-options: -W
+
+executable sv2v
+  default-language: Haskell2010
+  main-is: sv2v.hs
+  Build-Depends:
+    base
+  ghc-options:
+    -O3
+    -threaded
+    -rtsopts
+    -with-rtsopts=-N
+    -funbox-strict-fields
+    -Wall
+
+source-repository head
+  type:     git
+  location: git://github.com/zachjs/sv2v.git
+

sv2v.hs

+{- sv2v
+   Author: Zachary Snow <zach@zachjs.com>
+
+   conversion entry point
+-}
+
+import System.IO
+import System.Exit
+
+main :: IO ()
+main = do
+    let res = Left "unimplemented"
+    case res of
+        Left  err -> do
+            hPrint stderr err
+            exitFailure
+        Right _ -> do
+            exitSuccess

verilog.cabal

-name:    verilog
-version: 0.0.12
-
-category: Language, Hardware, Embedded
-
-synopsis: Verilog preprocessor, parser, and AST.
-
-description:
-  A parser and supporting a small subset of Verilog.
-  Intended for machine generated, synthesizable code.
-
-author:     Tom Hawkins <tomahawkins@gmail.com>
-maintainer: Tom Hawkins <tomahawkins@gmail.com>
-
-license:      BSD3
-license-file: LICENSE
-
-homepage: http://github.com/tomahawkins/verilog
-
-build-type:    Simple
-cabal-version: >= 1.10
-
-library
-  default-language: Haskell2010
-  build-tools:
-    alex  >= 3 && < 4,
-    happy >= 1 && < 2
-  build-depends:
-    base       >= 4.8.2.0   && < 5.0,
-    array      >= 0.5.1.0   && < 0.6
-
-  exposed-modules:
-    Data.BitVec
-    Language.Verilog
-    Language.Verilog.AST
-    Language.Verilog.Parser
-    Language.Verilog.Parser.Lex
-    Language.Verilog.Parser.Parse
-    Language.Verilog.Parser.Preprocess
-    Language.Verilog.Parser.Tokens
-
-  ghc-options: -W
-
-source-repository head
-  type:     git
-  location: git://github.com/tomahawkins/verilog.git
-