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  1. 04 Oct, 2013 9 commits
  3. 03 Oct, 2013 24 commits
    • re PR c++/19476 (Missed null checking elimination with new) · f0aaf8c1 
      2013-10-04  Marc Glisse  <marc.glisse@inria.fr>

	PR c++/19476
gcc/cp/
	* decl.c (cxx_init_decl_processing): Set operator_new_flag.

gcc/testsuite/
	* g++.dg/tree-ssa/pr19476-5.C: New file.
	* g++.dg/tree-ssa/pr19476-1.C: Mention pr19476-5.C.

From-SVN: r203194
      Marc Glisse committed
    • re PR c++/58584 ([c++11] ICE with invalid argument for alignas) · 2765f897 
      /cp
2013-10-04  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/58584
	* decl2.c (save_template_attributes): Handle error_mark_node as
	*attr_p argument.
	(cp_check_const_attributes): Likewise for attributes.
	* parser.c (cp_parser_std_attribute_spec): When alignas_expr is an
	error_mark_node call cp_parser_skip_to_end_of_statement.

/testsuite
2013-10-04  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/58584
	* g++.dg/cpp0x/gen-attrs-55.C: New.

From-SVN: r203193
      Paolo Carlini committed
    • * sr.po: Update. · d9d60b6f 
      From-SVN: r203191
      Joseph Myers committed
    • regex_executor.tcc (_DFSExecutor<>::_M_dfs): Fix wrong backup variable initialization. · 468146e0 
      2013-10-03  Tim Shen  <timshen91@gmail.com>

	* include/bits/regex_executor.tcc (_DFSExecutor<>::_M_dfs): Fix wrong
	backup variable initialization.

From-SVN: r203190
      Tim Shen committed
    • re PR libstdc++/58604 (Text truncation in comments of /usr/include/c++/4.7/vector) · d358f348 
      2013-10-03  John Woolverton  <jdwoolverton@gmail.com>

	PR libstdc++/58604
	* include/std/vector: Fix garbled line in HP Copyright.

From-SVN: r203187
      John Woolverton committed
    • re PR c++/33911 (attribute deprecated vs. templates) · d1f11e2b 
      2013-10-03  Easwaran Raman  <eraman@google.com>

        PR c++/33911
        * parser.c (cp_parser_init_declarator): Do not drop attributes
        of template member functions.

2013-10-03  Easwaran Raman  <eraman@google.com>

        PR c++/33911
        * g++.dg/ext/attribute47.C: New.

From-SVN: r203174
      Easwaran Raman committed
    • i386.c (ix86_issue_rate): Pentium4, Nocona has issue rate of 2. · 6867e128 
      	* i386.c (ix86_issue_rate): Pentium4, Nocona has issue rate of 2.
	Core2, Corei7 and Haswell has issue rate of 4.
	(ix86_adjust_cost): Remove ATOM case; fix core2/corei7/Haswell case.

From-SVN: r203172
      Jan Hubicka committed
    • i386.c (ix86_option_override_internal): Do not enable accumulate-outgoing-args… · c7f36d55 
      i386.c (ix86_option_override_internal): Do not enable accumulate-outgoing-args when producing unwind info.

	* i386.c (ix86_option_override_internal): Do not enable
	accumulate-outgoing-args when producing unwind info.

From-SVN: r203171
      Jan Hubicka committed
    • lra-constraints.c (insert_move_for_subreg): New function extracted from simplify_operand_subreg. · 4f0bee4c 
      2013-10-03  Wei Mi  <wmi@google.com>

        * lra-constraints.c (insert_move_for_subreg): New function
        extracted from simplify_operand_subreg.
        (simplify_operand_subreg): Add reload for paradoxical subreg.

From-SVN: r203169
      Wei Mi committed
    • ipa-inline-analysis.c (find_foldable_builtin_expect): Find the candidate of… · 111c3f39 
      ipa-inline-analysis.c (find_foldable_builtin_expect): Find the candidate of builtin_expect such that we should fix the size/time...

        * ipa-inline-analysis.c (find_foldable_builtin_expect): Find
        the candidate of builtin_expect such that we should fix the 
        size/time estimation.
        (estimate_function_body_sizes): Do the acutally size/time fix-up
        for builtin_expect.

From-SVN: r203168
      Rong Xu committed
    • predict.c (tree_predict_by_opcode): Get the probability for builtin_expect from… · 942df739 
      predict.c (tree_predict_by_opcode): Get the probability for builtin_expect from param builtin_expect_probability.

        * predict.c (tree_predict_by_opcode): Get the probability
        for builtin_expect from param builtin_expect_probability.
        * params.def (BUILTIN_EXPECT_PROBABILITY): New parameter.
        * predict.def (PRED_BUILTIN_EXPECT_RELAXED): Fix comments.
        * doc/invoke.texi: Add documentation for builtin-expect-probability.
        * gcc.target/i386/cold-attribute-2.c: Fix the test by using original
        probability.
        * gcc.dg/tree-ssa/ipa-split-5.c: Ditto.
        * gcc.dg/tree-ssa/ipa-split-6.c: Ditto.

--This li (t)ene, and those below, will be ignored--

M    gcc/params.def
M    gcc/predict.def
M    gcc/ChangeLog
M    gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c
M    gcc/testsuite/gcc.dg/tree-ssa/ipa-split-6.c
M    gcc/testsuite/gcc.target/i386/cold-attribute-2.c
M    gcc/predict.c
M    gcc/doc/invoke.texi

From-SVN: r203167
      Rong Xu committed
    • re PR c++/58510 ([c++11] ICE with multiple non-static data initializations in union) · 2ef7251f 
      	PR c++/58510
cp/
	* init.c (sort_mem_initializers): Splice when giving an error.
testsuite/
	* g++.dg/cpp0x/pr58510.C: New test.

From-SVN: r203165
      Marek Polacek committed
    • del_op.cc (operator delete): Don't test for 0 before free. · fc7657bb 
      2013-10-03  Marc Glisse  <marc.glisse@inria.fr>

	* libsupc++/del_op.cc (operator delete): Don't test for 0 before free.
	* libsupc++/del_opnt.cc (free): Only declare if freestanding.
	(operator delete): Qualify free with std::.

From-SVN: r203164
      Marc Glisse committed
    • re PR c++/19476 (Missed null checking elimination with new) · 2284b034 
      2013-10-03  Marc Glisse  <marc.glisse@inria.fr>

	PR c++/19476
gcc/c-family/
	* c.opt (fcheck-new): Move to common.opt.

gcc/
	* common.opt (fcheck-new): Moved from c.opt. Make it 'Common'.
	* calls.c (alloca_call_p): Use get_callee_fndecl.
	* fold-const.c (tree_expr_nonzero_warnv_p): Handle operator new.
	* tree-vrp.c (gimple_stmt_nonzero_warnv_p, stmt_interesting_for_vrp):
	Likewise.
	(vrp_visit_stmt): Remove duplicated code.

gcc/testsuite/
	* g++.dg/tree-ssa/pr19476-1.C: New file.
	* g++.dg/tree-ssa/pr19476-2.C: Likewise.
	* g++.dg/tree-ssa/pr19476-3.C: Likewise.
	* g++.dg/tree-ssa/pr19476-4.C: Likewise.

From-SVN: r203163
      Marc Glisse committed
    • rs6000-builtin.def (XSRDPIM): Use floatdf2, ceildf2, btruncdf2, instead of vsx_* name. · 0609bdf2 
      [gcc]
2013-10-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,
	ceildf2, btruncdf2, instead of vsx_* name.

	* config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic
	iterators to only do V2DF and V4SF here.  Move the DF code to
	rs6000.md where it is combined with SF mode.  Replace <VSv> with
	just 'v' since only vector operations are handled with these insns
	after moving the DF support to rs6000.md.
	(vsx_sub<mode>3): Likewise.
	(vsx_mul<mode>3): Likewise.
	(vsx_div<mode>3): Likewise.
	(vsx_fre<mode>2): Likewise.
	(vsx_neg<mode>2): Likewise.
	(vsx_abs<mode>2): Likewise.
	(vsx_nabs<mode>2): Likewise.
	(vsx_smax<mode>3): Likewise.
	(vsx_smin<mode>3): Likewise.
	(vsx_sqrt<mode>2): Likewise.
	(vsx_rsqrte<mode>2): Likewise.
	(vsx_fms<mode>4): Likewise.
	(vsx_nfma<mode>4): Likewise.
	(vsx_copysign<mode>3): Likewise.
	(vsx_btrunc<mode>2): Likewise.
	(vsx_floor<mode>2): Likewise.
	(vsx_ceil<mode>2): Likewise.
	(vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.
	(vsx_sminsf3): Likewise.
	(vsx_fmadf4): Likewise.
	(vsx_fmsdf4): Likewise.
	(vsx_nfmadf4): Likewise.
	(vsx_nfmsdf4): Likewise.
	(vsx_cmpdf_internal1): Likewise.

	* config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it
	simpler to select whether a target has SPE or traditional floating
	point support in iterators.
	(TARGET_DF_SPE): Likewise.
	(TARGET_SF_FPR): Likewise.
	(TARGET_DF_FPR): Likewise.
	(TARGET_SF_INSN): Macros to say whether floating point support
	exists for a given operation for expanders.
	(TARGET_DF_INSN): Likewise.

	* config/rs6000/rs6000.c (Ftrad): New mode attributes to allow
	combining of SF/DF mode operations, using both traditional and VSX
	registers.
	(Fvsx): Likewise.
	(Ff): Likewise.
	(Fv): Likewise.
	(Fs): Likewise.
	(Ffre): Likewise.
	(FFRE): Likewise.
	(abs<mode>2): Combine SF/DF modes using traditional floating point
	instructions.  Add support for using the upper DF registers with
	VSX support, and SF registers with power8-vector support.  Update
	expanders for operations supported by both the SPE and traditional
	floating point units.
	(abs<mode>2_fpr): Likewise.
	(nabs<mode>2): Likewise.
	(nabs<mode>2_fpr): Likewise.
	(neg<mode>2): Likewise.
	(neg<mode>2_fpr): Likewise.
	(add<mode>3): Likewise.
	(add<mode>3_fpr): Likewise.
	(sub<mode>3): Likewise.
	(sub<mode>3_fpr): Likewise.
	(mul<mode>3): Likewise.
	(mul<mode>3_fpr): Likewise.
	(div<mode>3): Likewise.
	(div<mode>3_fpr): Likewise.
	(sqrt<mode>3): Likewise.
	(sqrt<mode>3_fpr): Likewise.
	(fre<Fs>): Likewise.
	(rsqrt<mode>2): Likewise.
	(cmp<mode>_fpr): Likewise.
	(smax<mode>3): Likewise.
	(smin<mode>3): Likewise.
	(smax<mode>3_vsx): Likewise.
	(smin<mode>3_vsx): Likewise.
	(negsf2): Delete SF operations that are merged with DF.
	(abssf2): Likewise.
	(addsf3): Likewise.
	(subsf3): Likewise.
	(mulsf3): Likewise.
	(divsf3): Likewise.
	(fres): Likewise.
	(fmasf4_fpr): Likewise.
	(fmssf4_fpr): Likewise.
	(nfmasf4_fpr): Likewise.
	(nfmssf4_fpr): Likewise.
	(sqrtsf2): Likewise.
	(rsqrtsf_internal1): Likewise.
	(smaxsf3): Likewise.
	(sminsf3): Likewise.
	(cmpsf_internal1): Likewise.
	(copysign<mode>3_fcpsgn): Add VSX/power8-vector support.
	(negdf2): Delete DF operations that are merged with SF.
	(absdf2): Likewise.
	(nabsdf2): Likewise.
	(adddf3): Likewise.
	(subdf3): Likewise.
	(muldf3): Likewise.
	(divdf3): Likewise.
	(fred): Likewise.
	(rsqrtdf_internal1): Likewise.
	(fmadf4_fpr): Likewise.
	(fmsdf4_fpr): Likewise.
	(nfmadf4_fpr): Likewise.
	(nfmsdf4_fpr): Likewise.
	(sqrtdf2): Likewise.
	(smaxdf3): Likewise.
	(smindf3): Likewise.
	(cmpdf_internal1): Likewise.
	(lrint<mode>di2): Use TARGET_<MODE>_FPR macro.
	(btrunc<mode>2): Delete separate expander, and combine with the
	insn and add VSX instruction support.  Use TARGET_<MODE>_FPR.
	(btrunc<mode>2_fpr): Likewise.
	(ceil<mode>2): Likewise.
	(ceil<mode>2_fpr): Likewise.
	(floor<mode>2): Likewise.
	(floor<mode>2_fpr): Likewise.
	(fma<mode>4_fpr): Combine SF and DF fused multiply/add support.
	Add support for using the upper registers with VSX and
	power8-vector.  Move insns to be closer to the define_expands. On
	VSX systems, prefer the traditional form of FMA over the VSX
	version, since the traditional form allows the target not to
	overlap with the inputs.
	(fms<mode>4_fpr): Likewise.
	(nfma<mode>4_fpr): Likewise.
	(nfms<mode>4_fpr): Likewise.

[gcc/testsuite]
2013-10-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p8vector-fp.c: New test for floating point
	scalar operations when using -mupper-regs-sf and -mupper-regs-df.
	* gcc.target/powerpc/ppc-target-1.c: Update tests to allow either
	VSX scalar operations or the traditional floating point form of
	the instruction.
	* gcc.target/powerpc/ppc-target-2.c: Likewise.
	* gcc.target/powerpc/recip-3.c: Likewise.
	* gcc.target/powerpc/recip-5.c: Likewise.
	* gcc.target/powerpc/pr72747.c: Likewise.
	* gcc.target/powerpc/vsx-builtin-3.c: Likewise.

From-SVN: r203162
      Michael Meissner committed
    • aarch-common-protos.h (struct alu_cost_table): New. · 5bea0c6c 
      [gcc/]
2013-10-03  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            Richard Earnshaw  <richard.earnshaw@arm.com>

	* config/arm/aarch-common-protos.h (struct alu_cost_table): New.
	(struct mult_cost_table): Likewise.
	(struct mem_cost_table): Likewise.
	(struct fp_cost_table): Likewise.
	(struct vector_cost_table): Likewise.
	(cpu_cost_table): Likewise.
	* config/arm/arm.opt (mold-rts-costs): New option.
	(mnew-generic-costs): Likewise.
	* config/arm/arm.c (generic_extra_costs): New table.
	(cortexa15_extra_costs): Likewise.
	(arm_slowmul_tune): Use NULL as new costs.
	(arm_fastmul_tune): Likewise.
	(arm_strongarm_tune): Likewise.
	(arm_xscale_tune): Likewise.
	(arm_9e_tune): Likewise.
	(arm_v6t2_tune): Likewise.
	(arm_cortex_a5_tune): Likewise.
	(arm_cortex_a9_tune): Likewise.
	(arm_v6m_tune): Likewise.
	(arm_fa726te_tune): Likewise.
	(arm_cortex_a15_tune): Use cortex15_extra_costs.
	(arm_cortex_tune): Use generict_extra_costs.
	(shifter_op_p): New function.
	(arm_unspec_cost): Likewise.
	(LIBCALL_COST): Define.
	(arm_new_rtx_costs): New function.
	(arm_rtx_costs): Use arm_new_rtx_costs when core-specific
	table is available. Use old costs otherwise unless mnew-generic-costs
	is specified.
	* config/arm/arm-protos.h (tune_params): Add insn_extra_cost field.
	(cpu_cost_table): Declare.

Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>

From-SVN: r203160
      Kyrylo Tkachov committed
    • [AArch64] Fix PR58460 · 24c56925 
      PR58460, the add and sub shifted register instruction forms in AArch64
do not permit the stack register.  This patch removes k constraint
from the relevant patterns and adds reduced form of the test case.

From-SVN: r203157
      Marcus Shawcroft committed
    • [AArch64] Remove un-necessary secondary reload for addition to SP. · 2ab8f063 
      From-SVN: r203156
      Ian Bolton committed
    • predict.c (probably_never_executed): New function. · 79221839 
      2013-10-02  Teresa Johnson  <tejohnson@google.com>

	* predict.c (probably_never_executed): New function.
	(probably_never_executed_bb_p): Invoke probably_never_executed.
	(probably_never_executed_edge_p): Ditto.
	* bb-reorder.c (find_rarely_executed_basic_blocks_and_crossing_edges):
	Treat profile insanities conservatively.

From-SVN: r203152
      Teresa Johnson committed
    • config.host (hppa*64*-*-linux*): Define extra_parts. · 69778659 
      	* config.host (hppa*64*-*-linux*): Define extra_parts.
	(hppa*-*-linux*): Likewise.

From-SVN: r203151
      John David Anglin committed
    • config.gcc (hppa*64*-*-linux*): Don't add pa/t-linux to tmake_file. · d441afe0 
      	* config.gcc (hppa*64*-*-linux*): Don't add pa/t-linux to tmake_file.

From-SVN: r203148
      John David Anglin committed
    • lra-constraints.c (process_alt_operand): Calculate scratch_p and use it. · 80f466c4 
      2013-10-02  Vladimir Makarov  <vmakarov@redhat.com>

	* lra-constraints.c (process_alt_operand): Calculate scratch_p and
	use it.  Use smaller increase for scratch.  Don't increase reject
	for early clobber scratch.
	* lra-eliminations.c (eliminate_regs_in_insn): Remove all insns
	setting eliminated regs except setting fp from hfp.
	(lra_eliminate): Check lra_insn_recog_data on NULL.

From-SVN: r203147
      Vladimir Makarov committed
    • Daily bump. · 7cfbb5a2 
      From-SVN: r203146
      GCC Administrator committed
    • re PR target/58587 (Bootstrap error with ada with -mcpu=power7) · 6e228b4b 
      2013-10-02  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/58587
	* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off
	setting -mvsx-timode by default until the underlying problem is
	fixed.
	(RS6000_CPU, power7 defaults): Likewise.

From-SVN: r203142
      Michael Meissner committed
  5. 02 Oct, 2013 7 commits