P0490R0 GB 20: decomposition declaration should commit to tuple
	interpretation early
	* decl.c (get_tuple_size): Make static.  If inst is error_mark_node
	or non-complete type, return NULL_TREE, otherwise if
	lookup_qualified_name fails or doesn't fold into INTEGER_CST, return
	error_mark_node.
	(get_tuple_element_type, get_tuple_decomp_init): Make static.
	(cp_finish_decomp): Pass LOC to get_tuple_size.  If it returns
	error_mark_node, complain and fail.

	* g++.dg/cpp1z/decomp10.C (f1): Adjust expected diagnostics.

From-SVN: r243724

re PR c++/77585 (g++ incorrectly decides that member function is called without object in generic lambda)

	PR c++/77585
	* pt.c (instantiate_decl): Push to class scope lambda resides
	within when instantiating a generic lambda function.

	PR c++/77585
	* g++.dg/cpp1y/pr77585.C: New.

From-SVN: r243723

gcc/ChangeLog:
	PR preprocessor/78680
	PR preprocessor/78811
	* input.c (struct selftest::lexer_test): Add field
	m_implicitly_expect_EOF.
	(selftest::lexer_error_sink): New class.
	(selftest::lexer_error_sink::s_singleton): New global.
	(selftest::lexer_test::lexer_test): Initialize new field
	"m_implicitly_expect_EOF".
	(selftest::lexer_test::~lexer_test): Conditionalize the
	check for the EOF token on the new field.
	(selftest::test_lexer_string_locations_raw_string_unterminated):
	New function.
	(selftest::input_c_tests): Call the new test.

libcpp/ChangeLog:
	PR preprocessor/78680
	PR preprocessor/78811
	* lex.c (_cpp_lex_direct): Only determine the end-location of
	the token and build a range for non-reserved start locations.
	Do not do it for EOF tokens.

From-SVN: r243721

Using leaf_function_p in a backend is dangerous as it incorrectly returns
false if it is called while in a sequence (for example during prolog/epilog
generation).  Replace all uses with crtl->is_leaf as this is now initialized
early enough in ira.c.  This typically causes no code generation differences
unless there was a bug due to leaf_function_p returning the wrong value.

    gcc/
        * config/arm/arm.h (TARGET_BACKTRACE): Use crtl->is_leaf.
        * config/arm/arm.c (arm_option_check_internal): Improve comment.
        (thumb_force_lr_save): Use crtl->is_leaf.
        (arm_get_frame_offsets): Remove comment.  Use crtl->is_leaf.
        (thumb_far_jump_used_p): Remove comment.
        (arm_frame_pointer_required): Use crtl->is_leaf.

From-SVN: r243720

From-SVN: r243718

	* doc/extend.texi: Clean up @xref{...} uses.
	* doc/invoke.texi: Likewise.

From-SVN: r243717

Now we finally have the infrastructure in place we can now derive
details of the FPU from a CPU entry.  This patch enables this for the
existing cores that already have an explicit FPU in their product names.

	* arm-fpus.def: Add CNAME field to all FPU definitions.
	* genopt.sh: Use explicit enumeration tags for FPU entries.
	* arm-tables.opt: Regenerated.
	* arm.opt (mfpu): Provide initial value.
	* arm-opts.h (enum fpu_type): Build the enumeration from the list of
	available FPUs.  Add 'auto' entry on the end.
	* arm.c (arm_configure_build_target): Only do explicit configuration
	of the FPU features if the selected FPU is not 'auto'.
	(arm_option_override): Adjust initialization of arm_fpu_index.
	Emit an error if we have a hard float ABI request, but the processor
	does not support floating-point.
	(arm_option_print): Handle -mfpu=auto.
	(arm_valid_target_attribute_rec): Don't permit fpu=auto in pragmas
	or function attributes.
	(arm_identify_fpu_from_isa): Handle effective soft-float when
	the FPU is automatically detected.
	* arm-cores.def (arm1136jf-s): Add feature ISA_FP_DBL.
	(arm1176jzf-s): Likewise.
	(mpcore): Likewise.
	(arm1156t2f-s): Likewise.

From-SVN: r243716

Now that everything uses the new ISA features, we can remove the
FEATURES field from the FPU descriptions, along with all the macros
and definitions associated with it.

	* arm-fpus.def (ARM_FPU): Remove features field from all definitions.
	* arm.h (arm_fpu_feature_set): Delete typedef.
	(FPU_FL_NONE): Delete.
	(FPU_FL_NEON): Delete.
	(FPU_FL_FP16): Delete.
	(FPU_FL_CRYPTO): Delete.
	(FPU_FL_DBL): Delete.
	(FPU_FL_D32): Delete.
	(FPU_FL_VFPv2): Delete.
	(FPU_FL_VFPv3): Delete.
	(FPU_FL_VFPv4): Delete.
	(FPU_FL_VFPv5): Delete.
	(FPU_FL_AMRv8): Delete.
	(FPU_VFPv2): Delete.
	(FPU_VFPv3): Delete.
	(FPU_VFPv4): Delete.
	(FPU_VFPv5): Delete.
	(FPU_ARMv8): Delete.
	(FPU_DBL): Delete.
	(FPU_D32): Delete.
	(FPU_NEON): Delete.
	(FPU_CRYPTO): Delete.
	(FPU_FP16): Delete.
	(arm_fpu_desc): Delete features field.
	* arm.c (all_fpus): Don't initialize feature field.

From-SVN: r243715

Now that we can construct the build target isa from the cl_target_options
data we can use this to determine inlinability.  This eliminates the
final remaining use of the FPU features field.

	* arm.c (arm_can_inline_p): Use ISA features for determining
	inlinability.

From-SVN: r243714

It now becomes apparent that it would be better to use the the
cl_target_options as the basis for calling arm_configure_build_target;
it already contains exactly the same fields that we need.  I chose not
to rewrite the earlier patches as that would make the progression of
changes seem less logical than it currently is, with several early
changes having no immediate justification.

	* arm-protos.h (arm_configure_build_target): Change second argument
	to cl_target_options.
	* arm.c (arm_configure_build_target): Likewise.
	(arm_option_restore): Update accordingly.
	(arm_option_override): Create the target_option_default_node before
	calling arm_configure_build_target.  Use it in call of latter.
	Resynchronize after all other overrides have been calculated.
	(arm_valid_target_attribute_tree): Use the target options for
	reconfiguration.  Resynchronize after performing override checks.
	* arm-c.c (arm_pragma_target_parse): Use target optiosn from cur_tree
	to reconfigure the build target.

From-SVN: r243713

Now that the isa feature bits are all available in arm_active_target
we can use that for most of the feature tests that are needed.

	* arm.h (TARGET_VFPD32): Use arm_active_target.
	(TARGET_VFP3): Likewise.
	(TARGET_VFP5): Likewise.
	(TARGET_VFP_SINGLE): Likewise.
	(TARGET_VFP_DOUBLE): Likewise.
	(TARGET_NEON_FP16): Likewise.
	(TARGET_FP16): Likewise.
	(TARGET_FMA): Likewise.
	(TARGET_FPU_ARMV8): Likewise.
	(TARGET_CRYPTO): Likewise.
	(TARGET_NEON): Likewise.
	(TARGET_FPU_FEATURES): Delete.
	* arm.c (arm_option_check_internal): Check for iwmmxt conflict with
	Neon using arm_active_target.

From-SVN: r243712

Rather than assuming a specific fpu name has been selected, we work
out the FPU from the ISA properties.  This is necessary since once we
have default FPUs selected by the processor, there will be no explicit
entry in the table of fpus to refer to.

This also fixes a bug with the code I added recently to permit new
aliases for existing FPU names: the new names cannot be passed to the
assembler since it does not recognize them.  By mapping the ISA
features back to the canonical names we avoid having to teach the
assembler about the new names.

	* arm.h (TARGET_FPU_NAME): Delete.
	* arm.c (arm_identify_fpu_from_isa): New function.
	(arm_declare_function_name): Use it to get the name for the FPU.

From-SVN: r243711

Now that we can describe the FPU with the standard ISA bits we need to
initialize them.  However, the FPU settings can be changed with target build
attributes, so we also need to reset them if things change.  This requires
a bit of juggling about with the existing code to ensure that the active
target is reconfigured after each change to the target options.

	* arm-protos.h: Include sbitmap.h
	(arm_configure_build_target): Make public.
	* arm.c (arm_configure_build_target): Now not static.
	(arm_valid_target_attribute_rec): Move internal option check to...
	(arm_valid_target_attribute_tree0: ... here.  Also reconfingure the
	active target.
	(arm_override_options_after_change): Call arm_configure_build_target.
	(isa_all_fpubits): Renamed from isa_fpubits.
	(arm_option_restore): New function.
	(TARGET_OPTION_RESTORE): Register it.
	(arm_configure_build_target): Initialize the FPU capability bits in
	the isa.
	(arm_option_override): Move the code that forces the setting of the
	FPU option before the call to arm_configure_build_target.
	* arm.opt (march): Mark as Save.
	(mcpu, mtune): Likewise.
	* arm-c.c (arm_pragma_target_parse): Reconfigure the build target
	after pragmas change the target options.

From-SVN: r243710

Similar to the new CPU and architecture ISA feature lists, we now add
similar capabilities to each FPU description.  We don't use these yet,
that will come in later patches.  These follow the same style as the
newly modified flag sets, but use slightly different defaults that
more accurately reflect the ISA specifications.

	* arm-isa.h (isa_feature): Add bits for VFPv4, FPv5, fp16conv,
	fP_dbl, fp_d32 and fp_crypto.
	(ISA_ALL_FPU): Add all the new bits.
	(ISA_VFPv2, ISA_VFPv3, ISA_VFPv4, ISA_FPv5): New macros.
	(ISA_FP_ARMv8, ISA_FP_DBL, ISA_FP_D32, ISA_NEON, ISA_CRYPTO): Likewise.
	* arm-fpus.def: Add ISA features to all FPUs.
	* arm.h: (arm_fpu_desc): Add new field for ISA bits.
	* arm.c (all_fpus): Initialize it.
	* arm-tables.opt: Regenerated.

From-SVN: r243709

Similar to the main ISA, we convert the FPU revision into a set of feature
bits.  This permits a more complex set of capability relationships to be
expressed more easily.  For now we continue to use the traditional bitmasks.

	* arm.h (FPU_FL_VFPv2) New feature bit.
	(FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise.
	(FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper
	macros.
	(FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise.
	(TARGET_FPU_REV): Delete.
	(TARGET_VFP3): Use feature bits.
	(TARGET_VFP5): Likewise.
	(TARGET_FMA): Likewise.
	(TARGET_FPU_ARMV8): Likewise.
	(struct arm_fpu_desc): Delete rev field.
	* arm-fpus.def: Delete REV entry, use new feature bits and macros.
	* arm.c (all_fpus): Delete rev field.

From-SVN: r243708

Remove the VFP_REGS field by converting its meanings into flag
attributes.  The new flag attributes build on each other describing
increasing capabilities.  This allows us to do a better job when
inlining functions with differing requiremetns on the fpu environment:
we can now inline A into B if B has at least the same register set
properties as B (previously we required identical register set
properties).

	* arm.h (vfp_reg_type): Delete.
	(TARGET_FPU_REGS): Delete.
	(arm_fpu_desc): Delete regs field.
	(FPU_FL_NONE, FPU_FL_NEON, FPU_FL_FP16, FPU_FL_CRYPTO): Use unsigned
	values.
	(FPU_FL_DBL, FPU_FL_D32): Define.
	(TARGET_VFPD32): Use feature test.
	(TARGET_VFP_SINGLE): Likewise.
	(TARGET_VFP_DOUBLE): Likewise.
	* arm-fpus.def: Update all entries for new feature bits.
	* arm.c (all_fpus): Update initializer macro.
	(arm_can_inline_p): Remove test on fpu regs.

From-SVN: r243707

The arm_fp_model enumeration type has only had one useful value since
the FPA support was removed, and it's no-longer used anywhere.  This
patch just cleans that up by removing it.

	* arm.h (arm_fp_model): Delete.

From-SVN: r243706

Nothing uses the old feature sets now, so we can delete them entirely.

	* arm-cores.def: Remove FLAGS field from all core definitions.
	* arm-arches.def: Likewise.
	* arm-opts.h (enum processor_type): Remove FLAGS parameter from
	ARM_CORES macro.
	(arm_arch_core_flags): Likewise, plus ARM_ARCH macro.
	* arm-protos.h (FL_*): Delete.
	(arm_feature_set): Delete.
	(ARM_FSET_*): Delete.
	* arm.c (struct processors): Delete flags field.
	(all_cores): Delete FLAGS parameter from macro, don't initialize flags.
	(all architectures): Likewise.

From-SVN: r243705

This converts the recently added implicit -mthumb support code to use
the new data structures.  Since we have a very simple query and no
initialized copies of the sbitmaps, for now we simply scan the list of
features to look for the one of interest.

	* arm-opts.h (struct arm_arch_core_flag): Add new field ISA.
	Initialize it.
   	(arm_arch_core_flag): Delete flags field.
    	(arm_arch_core_flags): Don't initialize flags field.
 	* common/config/arm/arm-common.c (check_isa_bits_for): New function.
	(arm_target_thumb_only): Use new isa bits arrays.

From-SVN: r243704

This patch finishes the job of removing insn_flags and moves the logic
over to using the new data structures.  I've added a new boolean
variable to detect when we have ARMv7ve-like capabilities and thus
have 64-bit atomic operations since that would be a complex query and
expensive to do in full.  It might be better to add a specific bit to
the ISA data structures to indicate this capability directly.

	* arm-protos.h (insn_flags): Delete declaration.
	(arm_arch7ve): Declare.
	* arm.c (insn_flags): Delete.
	(arm_arch7ve): New variable.
	(arm_selected_cpu): Delete.
	(arm_option_check_internal): Use new ISA bitmap.
	(arm_option_override_internal): Likewise.
	(arm_configure_build_target): Declare arm_selected_cpu locally.
	(arm_option_override): Use new ISA bitmap.  Initialize arm_arch7ve.
	Rearrange variable intialization by general function.
	* arm.h (TARGET_HAVE_LPAE): Use arm_arch7ve.

From-SVN: r243703

This patch uses the new ISA data structure to determine which builtins
to add.  It entirely eliminates the need for insn_flags to be a global
variable, but we're about to delete that in the following patches, so
for now we leave it as a global.

	* arm-builtins.c: Include sbitmap.h.
	(def_mbuiltin): Change first parameter to a flag bit.  Use it to test
	available features in the current target.
	(struct builtin_description): Change type of feature field.
	(IWMMXT_BUILTIN): Use the isa_features types.
	(IWMMXT2_BUILTIN): Likewise.
	(IWMMXT_BUILTIN2): Likewise.
	(IWMMXT2_BUILTIN2): Likewise.
	(CRC32_BUILTIN): Likewise.
	(CRYPTO_BUILTIN): Likewise.
	(iwmmx_builtin): Likewise.
	(iwmmx2_builtin): Likewise.
	(arm_iwmmxt_builtin): Check for specific feature bits.

From-SVN: r243702

With the new data structures it is trivial to add a new field and we
aren't (too) limited as to the number we have.  This patch adds a new
bit to describe the need for a particular compiler behaviour
modification: in this case a quirk in the cortex-m3.

	* arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
	(ISA_ALL_QUIRKS): New macro.
	* arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
	* arm.c (isa_quirkbits): New feature-list bitmap.
	(arm_configure_build_target): Ignore quirk bits when comparing an
	architecture feature list with a CPU feature list.
	(arm_option_override): Initialize_isa_quirkbits.  If the user has
	not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
	feature if isa_quirk_cm3_ldrd appears in the isa feature list.

From-SVN: r243701

Make more use of the new data structure for initializing existing
variables.

	* arm.c (arm_option_override): Use arm_active_target as source of
	information for arm_base_arch and arm_arch_name.
	* (arm_file_start): Use arm_active_target for core name.

From-SVN: r243700

We now start to make more use of the new data structure.  This allows
us to eliminate two of the existing static variables,
arm_selected_arch and arm_selected tune.

	* arm.c (arm_selected_tune): Delete static variable.
	(arm_selected_arch): Likewise.
	(arm_configure_build_target): Declare local versions of arm_selected
	target and arm_selected_arch.  Initialize more fields in target
	data structure.
	(arm_option_override): Use arm_active_target instead of
	arm_selected_tune and arm_selected_arch.
	(asm_file_start): Use arm_active_target.

From-SVN: r243699

This patch creates a new data structure for carrying around the data
relating to the current compilation target.  The idea behind this is
that this data structure can be updated to reflect the overall
compilation target as new information is gathered (from command line
options) or architectural extensions.  We will no-longer have to grub
around looking in multiple places for this information.

There are some small behaviour changes around how we handle selecting
a default CPU if thumb or interworking are specified on the command
line and the default CPU does not support thumb, but I believe the
existing code was broken in that respect.  This code will go away once
we obsolete pre-armv4t devices.

	* arm-protos.h (arm_build_target): New structure.
	(arm_active_target): Declare it.
	* arm.c (arm_active_target): New variable.
	(bitmap_popcount): New function.
	(feature_count): Delete.
	(arm_initialize_isa): New function.
	isa_fpubits): New variable.
	(arm_configure_build_target): New function.
	(arm_option_override): Initialize isa_fpubits and arm_active_target.isa.
	Use arm_configure_build_target.

From-SVN: r243698

This patch adds the new ISA data structures.  The idea is to use an
sbitmap for carrying these around internally.  We don't make much use
of this yet, but will increasingly migrate over to this in the
following patches.  All cores and architectures currently have both
old and new encodings for now.

For simplicity and clarity we introduce internally the concept of
ARMv7ve.  It doesn't change any visible behaviour.

There's also a bit of tidying up of the various supported cores,
sorting them by profile.

	* arm-isa.h: New file.
	* arm-protos.h: Include it.
	* arm-arches.def: Add new ISA field to all entries.  Drop bogus
	armv8.1-a+crc architecture.
	* arm-cores.def: Similarly.  Group ARMv8 cores by profile.
	* arm-opts.h (enum processor_type): Adjust for new field.
	* arm.c (struct processors): New field 'isa_bits'.
	(all_cores, all_architectures): Initialize new field.
	* arm-tables.opt: Regenerated.
	* arm-tune.md: Regenerated.

From-SVN: r243697

We start out by separating the 'tuning flags' in a CPU or architecture
specification into a new field in the data structures.  Because there
aren't very many of these (and we'd like to get rid of them entirely,
eventually, moving to entries in the tuning tables), we just use a
simple unsigned word.  This frees up a number of bits in the main
flags data structure, but we don't consolidate them as we'll be
getting rid of them entirely shortly.

There's one small user-visible change, the slow multiply flag is moved
from being treated as an architectural flag to a tuning flag.  This
has two consequences: it's now ignored for architectural matching to a
CPU and specifying a -mtune option will now correctly apply the
multiply performance to the decision as to which sequences to
synthesise.

	* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
	tuning properties from architectural FLAGS field.
	* arm-cores.def (ARM_CORE): Likewise.
	* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
	(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
	(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
	(FL_TUNE): Remove deleted elements.
	(tune_flags): Convert type to unsigned int.
	* arm.c (struct processors): Add new field tune_flags.
	(all_cores, all_arches): Initialize it.
	(arm_option_override): Adapt uses of tune_flags.  Use tune_flags
	for deciding when we should have slow multiply operations.

From-SVN: r243696

From-SVN: r243695

        * gcc.dg/tree-ssa/ssa-fre-55.c: Add -Wno-psabi.
        * gcc.dg/tree-ssa/pr71179.c: Same.

From-SVN: r243694

	PR libstdc++/59170
	* python/libstdcxx/v6/printers.py (StdListIteratorPrinter.to_string)
	(StdSlistIteratorPrinter.to_string, StdVectorIteratorPrinter.to_string)
	(StdRbtreeIteratorPrinter.to_string)
	(StdDequeIteratorPrinter.to_string): Add check for value-initialized
	iterators.
	* testsuite/libstdc++-prettyprinters/simple.cc: Test them.
	* testsuite/libstdc++-prettyprinters/simple11.cc: Likewise.

From-SVN: r243692

2016-12-15  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/78800
	* interface.c (compare_allocatable): Avoid additional errors on bad
	class declarations.
	(compare_parameter): Put the result of gfc_expr_attr into a variable,
	in order to avoid calling it multiple times. Exit early on bad class
	declarations to avoid ICE.

2016-12-15  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/78800
	* gfortran.dg/unlimited_polymorphic_27.f90: New test case.

From-SVN: r243691

	PR libstdc++/59161
	* python/libstdcxx/v6/printers.py (StdListIteratorPrinter.to_string)
	(StdSlistIteratorPrinter.to_string, StdVectorIteratorPrinter.to_string)
	(StdRbtreeIteratorPrinter.to_string, StdDequeIteratorPrinter.to_string)
	(StdDebugIteratorPrinter.to_string): Return string instead of
	gdb.Value.
	* testsuite/libstdc++-prettyprinters/59161.cc: New test.

From-SVN: r243690

	* python/libstdcxx/v6/printers.py (UniquePointerPrinter.to_string):
	Remove redundant parentheses.
	(RbtreeIterator, StdRbtreeIteratorPrinter): Add docstrings.
	(StdForwardListPrinter.to_string): Remove redundant parentheses.
	(StdExpOptionalPrinter.to_string): Use string formatting instead of
	concatenation.
	(StdVariantPrinter.to_string, StdNodeHandlePrinter.to_string)
	(TemplateTypePrinter): Adjust whitespace.

From-SVN: r243689

	* python/libstdcxx/v6/xmethods.py (UniquePtrGetWorker.__init__): Use
	correct element type for unique_ptr<T[]>.
	(UniquePtrGetWorker._supports, UniquePtrDerefWorker._supports): New
	functions to disable unsupported operators for unique_ptr<T[]>.
	(UniquePtrSubscriptWorker): New worker for operator[].
	(UniquePtrMethodsMatcher.__init__): Register UniquePtrSubscriptWorker.
	(UniquePtrMethodsMatcher.match): Call _supports on the chosen worker.
	(SharedPtrGetWorker, SharedPtrDerefWorker, SharedPtrSubscriptWorker)
	(SharedPtrUseCountWorker, SharedPtrUniqueWorker): New workers.
	(SharedPtrMethodsMatcher): New matcher for shared_ptr.
	(register_libstdcxx_xmethods): Register SharedPtrMethodsMatcher.
	* testsuite/libstdc++-xmethods/unique_ptr.cc: Test arrays.
	* testsuite/libstdc++-xmethods/shared_ptr.cc: New test.

From-SVN: r243688

gcc/testsuite

	* gcc.target/mips/mips.exp (mips-dg-options): Upgrade to R2 for
	-mmicromips.

From-SVN: r243687

	* gcc.dg/tree-ssa/forwprop-35.c: Use -Wno-psabi everywhere.
	* gcc.dg/torture/pr78515.c: Likewise.
	* gcc.dg/pr69634.c: Likewise.

From-SVN: r243686

gcc/ChangeLog:

	PR middle-end/78519
	* gimple-ssa-sprintf.c (format_string): Handle null pointers.
	(format_directive): Diagnose null pointer arguments.
	(pass_sprintf_length::handle_gimple_call): Diagnose null destination
	pointers.  Correct location of null format string in diagnostics.

gcc/testsuite/ChangeLog:

	PR middle-end/78519
	* gcc.dg/tree-ssa/builtin-sprintf-warn-7.c: New test.

From-SVN: r243684

gcc/cp/ChangeLog:

	PR c++/78774
	* pt.c (convert_template_argument): Avoid assuming operand type
	is non-null since that of SCOPE_REF is not.

gcc/testsuite/ChangeLog:

	PR c++/78774
	* g++.dg/cpp1y/pr78774.C: New test.

From-SVN: r243683

    
    Prune away a bit of unnecessary code from the helper routine
    Slice_construction_expression::create_array_val() that was adding
    an extra NULL value to empty slices (no longer needed).
    
    Reviewed-on: https://go-review.googlesource.com/34410

From-SVN: r243682

gcc/ChangeLog:
	* Makefile.in (SELFTEST_FLAGS): Add path argument to -fself-test.
	(s-selftest): Add dependency on the selftests data directory.
	* common.opt (fself-test): Rename to...
	(fself-test=): ...this, documenting the meaning of the argument.
	* selftest-run-tests.c (along): Likewise.
	* selftest-run-tests.c: Include "options.h".
	(selftest::run_tests): Initialize selftest::path_to_selftest_files
	from flag_self_test.
	* selftest.c (selftest::path_to_selftest_files): New global.
	(selftest::locate_file): New function.
	(selftest::test_locate_file): New function.
	(selftest_c_tests): Likewise.
	(selftest::selftest_c_tests): Call test_locate_file.
	* selftest.h (selftest::locate_file): New decl.
	(selftest::path_to_selftest_files): New decl.

gcc/testsuite/ChangeLog:
	PR target/78213
	* gcc.dg/cpp/pr71591.c: Add a fake value for the argument of
	-fself-test.
	* gcc.dg/pr78213.c: Disable this test.
	* selftests/example.txt: New file.

From-SVN: r243681