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riscv-gcc-1
Commit c17c0c7a by Richard Earnshaw Committed by Richard Earnshaw
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[arm] Remove FPU rev field 

Similar to the main ISA, we convert the FPU revision into a set of feature
bits.  This permits a more complex set of capability relationships to be
expressed more easily.  For now we continue to use the traditional bitmasks.

	* arm.h (FPU_FL_VFPv2) New feature bit.
	(FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise.
	(FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper
	macros.
	(FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise.
	(TARGET_FPU_REV): Delete.
	(TARGET_VFP3): Use feature bits.
	(TARGET_VFP5): Likewise.
	(TARGET_FMA): Likewise.
	(TARGET_FPU_ARMV8): Likewise.
	(struct arm_fpu_desc): Delete rev field.
	* arm-fpus.def: Delete REV entry, use new feature bits and macros.
	* arm.c (all_fpus): Delete rev field.

From-SVN: r243708
parent 3d7f68c6
Showing with 62 additions and 30 deletions
gcc/ChangeLog
2016-12-15 Richard Earnshaw <rearnsha@arm.com>
* arm.h (FPU_FL_VFPv2) New feature bit.
(FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise.
(FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper
macros.
(FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise.
(TARGET_FPU_REV): Delete.
(TARGET_VFP3): Use feature bits.
(TARGET_VFP5): Likewise.
(TARGET_FMA): Likewise.
(TARGET_FPU_ARMV8): Likewise.
(struct arm_fpu_desc): Delete rev field.
* arm-fpus.def: Delete REV entry, use new feature bits and macros.
* arm.c (all_fpus): Delete rev field.
2016-12-15 Richard Earnshaw <rearnsha@arm.com>
* arm.h (vfp_reg_type): Delete.
(TARGET_FPU_REGS): Delete.
(arm_fpu_desc): Delete regs field.
gcc/config/arm/arm-fpus.def
......@@ -19,31 +19,31 @@
/* Before using #include to read this file, define a macro:
ARM_FPU(NAME, REV, FEATURES)
ARM_FPU(NAME, FEATURES)
The arguments are the fields of struct arm_fpu_desc.
genopt.sh assumes no whitespace up to the first "," in each entry. */
ARM_FPU("vfp", 2, FPU_FL_DBL)
ARM_FPU("vfpv2", 2, FPU_FL_DBL)
ARM_FPU("vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL)
ARM_FPU("vfpv3-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
ARM_FPU("vfpv3-d16", 3, FPU_FL_DBL)
ARM_FPU("vfpv3-d16-fp16", 3, FPU_FL_DBL | FPU_FL_FP16)
ARM_FPU("vfpv3xd", 3, FPU_FL_NONE)
ARM_FPU("vfpv3xd-fp16", 3, FPU_FL_FP16)
ARM_FPU("neon", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON)
ARM_FPU("neon-vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON)
ARM_FPU("neon-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
ARM_FPU("vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
ARM_FPU("vfpv4-d16", 4, FPU_FL_DBL | FPU_FL_FP16)
ARM_FPU("fpv4-sp-d16", 4, FPU_FL_FP16)
ARM_FPU("fpv5-sp-d16", 5, FPU_FL_FP16)
ARM_FPU("fpv5-d16", 5, FPU_FL_DBL | FPU_FL_FP16)
ARM_FPU("neon-vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
ARM_FPU("fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
ARM_FPU("neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
ARM_FPU("crypto-neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
ARM_FPU("vfp", FPU_VFPv2 | FPU_DBL)
ARM_FPU("vfpv2", FPU_VFPv2 | FPU_DBL)
ARM_FPU("vfpv3", FPU_VFPv3 | FPU_D32)
ARM_FPU("vfpv3-fp16", FPU_VFPv3 | FPU_D32 | FPU_FP16)
ARM_FPU("vfpv3-d16", FPU_VFPv3 | FPU_DBL)
ARM_FPU("vfpv3-d16-fp16", FPU_VFPv3 | FPU_DBL | FPU_FP16)
ARM_FPU("vfpv3xd", FPU_VFPv3)
ARM_FPU("vfpv3xd-fp16", FPU_VFPv3 | FPU_FP16)
ARM_FPU("neon", FPU_VFPv3 | FPU_NEON)
ARM_FPU("neon-vfpv3", FPU_VFPv3 | FPU_NEON)
ARM_FPU("neon-fp16", FPU_VFPv3 | FPU_NEON | FPU_FP16)
ARM_FPU("vfpv4", FPU_VFPv4 | FPU_D32 | FPU_FP16)
ARM_FPU("vfpv4-d16", FPU_VFPv4 | FPU_DBL | FPU_FP16)
ARM_FPU("fpv4-sp-d16", FPU_VFPv4 | FPU_FP16)
ARM_FPU("fpv5-sp-d16", FPU_VFPv5 | FPU_FP16)
ARM_FPU("fpv5-d16", FPU_VFPv5 | FPU_DBL | FPU_FP16)
ARM_FPU("neon-vfpv4", FPU_VFPv4 | FPU_NEON | FPU_FP16)
ARM_FPU("fp-armv8", FPU_ARMv8 | FPU_D32 | FPU_FP16)
ARM_FPU("neon-fp-armv8", FPU_ARMv8 | FPU_NEON | FPU_FP16)
ARM_FPU("crypto-neon-fp-armv8", FPU_ARMv8 | FPU_CRYPTO | FPU_FP16)
/* Compatibility aliases. */
ARM_FPU("vfp3", 3, FPU_FL_D32 | FPU_FL_DBL)
ARM_FPU("vfp3", FPU_VFPv3 | FPU_D32)
gcc/config/arm/arm.c
......@@ -2323,8 +2323,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
const struct arm_fpu_desc all_fpus[] =
{
#define ARM_FPU(NAME, REV, FEATURES) \
{ NAME, REV, FEATURES },
#define ARM_FPU(NAME, FEATURES) \
{ NAME, FEATURES },
#include "arm-fpus.def"
#undef ARM_FPU
};
......
gcc/config/arm/arm.h
......@@ -164,10 +164,10 @@ extern tree arm_fp16_type_node;
#define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32)
/* FPU supports VFPv3 instructions. */
#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
#define TARGET_VFP3 (TARGET_FPU_FEATURES & FPU_FL_VFPv3)
/* FPU supports FPv5 instructions. */
#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
#define TARGET_VFP5 (TARGET_FPU_FEATURES & FPU_FL_VFPv5)
/* FPU only supports VFP single-precision instructions. */
#define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0)
......@@ -190,10 +190,10 @@ extern tree arm_fp16_type_node;
(TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5))
/* FPU supports fused-multiply-add operations. */
#define TARGET_FMA (TARGET_FPU_REV >= 4)
#define TARGET_FMA (TARGET_FPU_FEATURES & FPU_FL_VFPv4)
/* FPU is ARMv8 compatible. */
#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8)
#define TARGET_FPU_ARMV8 (TARGET_FPU_FEATURES & FPU_FL_ARMv8)
/* FPU supports Crypto extensions. */
#define TARGET_CRYPTO \
......@@ -341,18 +341,34 @@ typedef unsigned long arm_fpu_feature_set;
#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */
#define FPU_FL_DBL (1u << 3) /* Has double precision. */
#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */
#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */
#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */
#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */
#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */
#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */
/* Some useful combinations. */
#define FPU_VFPv2 (FPU_FL_VFPv2)
#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3)
#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4)
#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5)
#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8)
#define FPU_DBL (FPU_FL_DBL)
#define FPU_D32 (FPU_DBL | FPU_FL_D32)
#define FPU_NEON (FPU_D32 | FPU_FL_NEON)
#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO)
#define FPU_FP16 (FPU_FL_FP16)
extern const struct arm_fpu_desc
{
const char *name;
int rev;
arm_fpu_feature_set features;
} all_fpus[];
/* Accessors. */
#define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name)
#define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev)
#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
/* Which floating point hardware to schedule for. */
......
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