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Commit 643a5717 by Richard Earnshaw Committed by Richard Earnshaw
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We start out by separating the 'tuning flags' in a CPU or architecture... 

We start out by separating the 'tuning flags' in a CPU or architecture
specification into a new field in the data structures.  Because there
aren't very many of these (and we'd like to get rid of them entirely,
eventually, moving to entries in the tuning tables), we just use a
simple unsigned word.  This frees up a number of bits in the main
flags data structure, but we don't consolidate them as we'll be
getting rid of them entirely shortly.

There's one small user-visible change, the slow multiply flag is moved
from being treated as an architectural flag to a tuning flag.  This
has two consequences: it's now ignored for architectural matching to a
CPU and specifying a -mtune option will now correctly apply the
multiply performance to the decision as to which sequences to
synthesise.

	* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
	tuning properties from architectural FLAGS field.
	* arm-cores.def (ARM_CORE): Likewise.
	* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
	(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
	(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
	(FL_TUNE): Remove deleted elements.
	(tune_flags): Convert type to unsigned int.
	* arm.c (struct processors): Add new field tune_flags.
	(all_cores, all_arches): Initialize it.
	(arm_option_override): Adapt uses of tune_flags.  Use tune_flags
	for deciding when we should have slow multiply operations.

From-SVN: r243696
parent f69f6aae
Showing with 87 additions and 74 deletions
gcc/ChangeLog
2016-12-15 Richard Earnshaw <rearnsha@arm.com>
* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
tuning properties from architectural FLAGS field.
* arm-cores.def (ARM_CORE): Likewise.
* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
(FL_TUNE): Remove deleted elements.
(tune_flags): Convert type to unsigned int.
* arm.c (struct processors): Add new field tune_flags.
(all_cores, all_arches): Initialize it.
(arm_option_override): Adapt uses of tune_flags. Use tune_flags
for deciding when we should have slow multiply operations.
2016-12-14 Martin Sebor <msebor@redhat.com>
PR middle-end/78519
gcc/common/config/arm/arm-common.c
......@@ -107,12 +107,12 @@ struct arm_arch_core_flag
static const struct arm_arch_core_flag arm_arch_core_flags[] =
{
#undef ARM_CORE
#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
{NAME, FLAGS},
#include "config/arm/arm-cores.def"
#undef ARM_CORE
#undef ARM_ARCH
#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \
{NAME, FLAGS},
#include "config/arm/arm-arches.def"
#undef ARM_ARCH
......
gcc/config/arm/arm-arches.def
......@@ -19,7 +19,7 @@
/* Before using #include to read this file, define a macro:
ARM_ARCH(NAME, CORE, ARCH, FLAGS)
ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS)
The NAME is the name of the architecture, represented as a string
constant. The CORE is the identifier for a core representative of
......@@ -28,52 +28,41 @@
genopt.sh assumes no whitespace up to the first "," in each entry. */
ARM_ARCH("armv2", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
ARM_ARCH("armv2a", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
ARM_ARCH("armv3", arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3))
ARM_ARCH("armv3m", arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M))
ARM_ARCH("armv4", arm7tdmi, 4, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4))
ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
ARM_ARCH("armv4t", arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T))
ARM_ARCH("armv5", arm10tdmi, 5, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5))
ARM_ARCH("armv5t", arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5T))
ARM_ARCH("armv5e", arm1026ejs, 5E, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5E))
ARM_ARCH("armv5te", arm1026ejs, 5TE, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5TE))
ARM_ARCH("armv6", arm1136js, 6, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6))
ARM_ARCH("armv6j", arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6J))
ARM_ARCH("armv6k", mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6K))
ARM_ARCH("armv6z", arm1176jzs, 6Z, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6Z))
ARM_ARCH("armv6kz", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6KZ))
ARM_ARCH("armv6zk", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6KZ))
ARM_ARCH("armv6t2", arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6T2))
ARM_ARCH("armv6-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
ARM_ARCH("armv6s-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
ARM_ARCH("armv7", cortexa8, 7, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7))
ARM_ARCH("armv7-a", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7A))
ARM_ARCH("armv7ve", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7VE))
ARM_ARCH("armv7-r", cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7R))
ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7M))
ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7EM))
ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH8A))
ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A))
ARM_ARCH("armv8.1-a", cortexa53, 8A,
ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
FL2_FOR_ARCH8_1A))
ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
FL2_FOR_ARCH8_1A))
ARM_ARCH ("armv8.2-a", cortexa53, 8A,
ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
FL2_FOR_ARCH8_2A))
ARM_ARCH ("armv8.2-a+fp16", cortexa53, 8A,
ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
FL2_FOR_ARCH8_2A | FL2_FP16INST))
ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
ARM_ARCH("armv6-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A))
ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
ARM_ARCH("armv8.1-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
gcc/config/arm/arm-flags.h
......@@ -22,6 +22,16 @@
#ifndef GCC_ARM_FLAGS_H
#define GCC_ARM_FLAGS_H
/* Flags used to identify a few tuning properties. These are for legacy
purposes only. Do not add any more of these: use the main tuning tables. */
#define TF_LDSCHED (1U << 0)
#define TF_WBUF (1U << 1)
#define TF_CO_PROC (1U << 2)
#define TF_SMALLMUL (1U << 3)
#define TF_STRONG (1U << 4)
#define TF_XSCALE (1U << 5)
#define TF_NO_MODE32 (1U << 6)
/* Flags used to identify the presence of processor capabilities. */
/* Bit values used to identify processor capabilities. */
......@@ -34,16 +44,15 @@
#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
#define FL_THUMB (1U << 6) /* Thumb aware. */
#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */
#define FL_STRONG (1U << 8) /* StrongARM. */
/* Spare (1U << 7) */
/* Spare (1U << 8) */
#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
#define FL_XSCALE (1U << 10) /* XScale. */
/* spare (1U << 11) */
/* Spare (1U << 11) */
#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
#define FL_WBUF (1U << 14) /* Schedule for write buffer ops.
Note: ARM6 & 7 derivatives only. */
/* Spare (1U << 14) */
#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
#define FL_THUMB2 (1U << 16) /* Thumb-2. */
#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
......@@ -57,7 +66,7 @@
#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
#define FL_ARCH8 (1U << 24) /* Architecture 8. */
#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */
/* Spare (1U << 26) */
#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
......@@ -73,8 +82,7 @@
#define FL2_CMSE (1U << 3) /* ARMv8-M Security Extensions. */
/* Flags that only effect tuning, not available instructions. */
#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
| FL_CO_PROC)
#define FL_TUNE (FL_VFPV2)
#define FL_FOR_ARCH2 FL_NOTM
#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
......
gcc/config/arm/arm-opts.h
......@@ -31,7 +31,7 @@
enum processor_type
{
#undef ARM_CORE
#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
TARGET_CPU_##INTERNAL_IDENT,
#include "arm-cores.def"
#undef ARM_CORE
......
gcc/config/arm/arm-protos.h
......@@ -358,7 +358,7 @@ extern arm_feature_set insn_flags;
/* The bits in this mask specify which instruction scheduling options should
be used. */
extern arm_feature_set tune_flags;
extern unsigned int tune_flags;
/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
extern int arm_arch3m;
......
gcc/config/arm/arm.c
......@@ -785,7 +785,7 @@ arm_feature_set insn_flags = ARM_FSET_EMPTY;
/* The bits in this mask specify which instruction scheduling options should
be used. */
arm_feature_set tune_flags = ARM_FSET_EMPTY;
unsigned int tune_flags = 0;
/* The highest ARM architecture version supported by the
target. */
......@@ -950,6 +950,7 @@ struct processors
{
const char *const name;
enum processor_type core;
unsigned int tune_flags;
const char *arch;
enum base_architecture base_arch;
const arm_feature_set flags;
......@@ -2287,12 +2288,12 @@ const struct tune_params arm_fa726te_tune =
static const struct processors all_cores[] =
{
/* ARM Cores */
#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
{NAME, TARGET_CPU_##IDENT, #ARCH, BASE_ARCH_##ARCH, \
#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
{NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
FLAGS, &arm_##COSTS##_tune},
#include "arm-cores.def"
#undef ARM_CORE
{NULL, TARGET_CPU_arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
{NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
};
static const struct processors all_architectures[] =
......@@ -2301,11 +2302,11 @@ static const struct processors all_architectures[] =
/* We don't specify tuning costs here as it will be figured out
from the core. */
#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
{NAME, TARGET_CPU_##CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \
{NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
#include "arm-arches.def"
#undef ARM_ARCH
{NULL, TARGET_CPU_arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
{NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
};
......@@ -3177,7 +3178,7 @@ arm_option_override (void)
arm_base_arch = arm_selected_cpu->base_arch;
arm_tune = arm_selected_tune->core;
tune_flags = arm_selected_tune->flags;
tune_flags = arm_selected_tune->tune_flags;
current_tune = arm_selected_tune->tune;
/* TBD: Dwarf info for apcs frame is not handled yet. */
......@@ -3228,10 +3229,10 @@ arm_option_override (void)
arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
arm_ld_sched = ARM_FSET_HAS_CPU1 (tune_flags, FL_LDSCHED);
arm_tune_strongarm = ARM_FSET_HAS_CPU1 (tune_flags, FL_STRONG);
arm_tune_wbuf = ARM_FSET_HAS_CPU1 (tune_flags, FL_WBUF);
arm_tune_xscale = ARM_FSET_HAS_CPU1 (tune_flags, FL_XSCALE);
arm_ld_sched = (tune_flags & TF_LDSCHED) != 0;
arm_tune_strongarm = (tune_flags & TF_STRONG) != 0;
arm_tune_wbuf = (tune_flags & TF_WBUF) != 0;
arm_tune_xscale = (tune_flags & TF_XSCALE) != 0;
arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT);
arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2);
arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV);
......@@ -3240,7 +3241,7 @@ arm_option_override (void)
arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0;
arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE);
arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL);
arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0;
arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST);
if (arm_fp16_inst)
{
......@@ -3324,7 +3325,7 @@ arm_option_override (void)
/* For arm2/3 there is no need to do any scheduling if we are doing
software floating-point. */
if (TARGET_SOFT_FLOAT && !ARM_FSET_HAS_CPU1 (tune_flags, FL_MODE32))
if (TARGET_SOFT_FLOAT && (tune_flags & TF_NO_MODE32))
flag_schedule_insns = flag_schedule_insns_after_reload = 0;
/* Use the cp15 method if it is available. */
......
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