2016-11-22  Jakub Jelinek  <jakub@redhat.com>
            Alexander Monakov  <amonakov@ispras.ru>

	* internal-fn.c (expand_GOMP_USE_SIMT): New function.
	* tree.c (omp_clause_num_ops): OMP_CLAUSE__SIMT_ has 0 operands.
	(omp_clause_code_name): Add _simt_ name.
	(walk_tree_1): Handle OMP_CLAUSE__SIMT_.
	* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE__SIMT_.
	* omp-low.c (scan_sharing_clauses): Handle OMP_CLAUSE__SIMT_.
	(scan_omp_simd): New function.
	(scan_omp_1_stmt): Use it in target regions if needed.
	(omp_max_vf): Don't max with omp_max_simt_vf.
	(lower_rec_simd_input_clauses): Use omp_max_simt_vf if
	OMP_CLAUSE__SIMT_ is present.
	(lower_rec_input_clauses): Compute maybe_simt from presence of
	OMP_CLAUSE__SIMT_.
	(lower_lastprivate_clauses): Likewise.
	(expand_omp_simd): Likewise.
	(execute_omp_device_lower): Lower IFN_GOMP_USE_SIMT.
	* internal-fn.def (GOMP_USE_SIMT): New internal function.
	* tree-pretty-print.c (dump_omp_clause): Handle OMP_CLAUSE__SIMT_.

Co-Authored-By: Alexander Monakov <amonakov@ispras.ru>

From-SVN: r242714

From-SVN: r242711

	* internal-fn.c (expand_GOMP_SIMT_LANE): New.
	(expand_GOMP_SIMT_VF): New.
	(expand_GOMP_SIMT_LAST_LANE): New.
	(expand_GOMP_SIMT_ORDERED_PRED): New.
	(expand_GOMP_SIMT_VOTE_ANY): New.
	(expand_GOMP_SIMT_XCHG_BFLY): New.
	(expand_GOMP_SIMT_XCHG_IDX): New.
	* internal-fn.def (GOMP_SIMT_LANE): New.
	(GOMP_SIMT_VF): New.
	(GOMP_SIMT_LAST_LANE): New.
	(GOMP_SIMT_ORDERED_PRED): New.
	(GOMP_SIMT_VOTE_ANY): New.
	(GOMP_SIMT_XCHG_BFLY): New.
	(GOMP_SIMT_XCHG_IDX): New.
	* omp-low.c (omp_maybe_offloaded_ctx): New, outlined from...
	(create_omp_child_function): ...here.  Set "omp target entrypoint"
	or "omp declare target" attribute based on is_gimple_omp_offloaded.
	(omp_max_simt_vf): New.  Use it...
	(omp_max_vf): ...here.
	(lower_rec_input_clauses): Add reduction lowering for SIMT execution.
	(lower_lastprivate_clauses): Likewise, for "lastprivate" lowering.
	(lower_omp_ordered): Likewise, for "ordered" lowering.
	(expand_omp_simd): Add SIMT transforms.
	(pass_data_lower_omp): Add PROP_gimple_lomp_dev.
	(execute_omp_device_lower): New.
	(pass_data_omp_device_lower): New.
	(pass_omp_device_lower): New pass.
	(make_pass_omp_device_lower): New.
	* passes.def (pass_omp_device_lower): Position new pass.
	* tree-pass.h (PROP_gimple_lomp_dev): Define.
	(make_pass_omp_device_lower): Declare.

From-SVN: r242710

re PR target/78451 (FAIL: gcc.target/i386/sse-22a.c: error: inlining failed in call to always_inline '_mm512_setzero_ps')

	PR target/78451
	* gcc.target/i386/sse-22.c: Add avx5124fmaps,avx5124vnniw to
	GCC target pragma before including immintrin.h.

From-SVN: r242708

re PR target/78451 (FAIL: gcc.target/i386/sse-22a.c: error: inlining failed in call to always_inline '_mm512_setzero_ps')

	PR target/78451
	* config/i386/avx512vlintrin.h (_mm_setzero_di): Removed.
	(_mm_maskz_mov_epi64): Use _mm_setzero_si128 instead of
	_mm_setzero_di.
	(_mm_maskz_load_epi64): Likewise.
	(_mm_setzero_hi): Removed.
	(_mm_maskz_loadu_epi64): Use _mm_setzero_si128 instead of
	_mm_setzero_di.
	(_mm_abs_epi64, _mm_maskz_abs_epi64, _mm_maskz_srl_epi64,
	_mm_maskz_unpackhi_epi64, _mm_maskz_unpacklo_epi64,
	_mm_maskz_compress_epi64, _mm_srav_epi64, _mm_maskz_srav_epi64,
	_mm_maskz_sllv_epi64, _mm_maskz_srlv_epi64, _mm_rolv_epi64,
	_mm_maskz_rolv_epi64, _mm_rorv_epi64, _mm_maskz_rorv_epi64,
	_mm_min_epi64, _mm_max_epi64, _mm_max_epu64, _mm_min_epu64,
	_mm_lzcnt_epi64, _mm_maskz_lzcnt_epi64, _mm_conflict_epi64,
	_mm_maskz_conflict_epi64, _mm_sra_epi64, _mm_maskz_sra_epi64,
	_mm_maskz_sll_epi64, _mm_rol_epi64, _mm_maskz_rol_epi64,
	_mm_ror_epi64, _mm_maskz_ror_epi64, _mm_alignr_epi64,
	_mm_maskz_alignr_epi64, _mm_srai_epi64, _mm_maskz_slli_epi64):
	Likewise.
	(_mm_cvtepi32_epi8, _mm256_cvtepi32_epi8, _mm_cvtsepi32_epi8,
	_mm256_cvtsepi32_epi8, _mm_cvtusepi32_epi8, _mm256_cvtusepi32_epi8,
	_mm_cvtepi32_epi16, _mm256_cvtepi32_epi16, _mm_cvtsepi32_epi16,
	_mm256_cvtsepi32_epi16, _mm_cvtusepi32_epi16, _mm256_cvtusepi32_epi16,
	_mm_cvtepi64_epi8, _mm256_cvtepi64_epi8, _mm_cvtsepi64_epi8,
	_mm256_cvtsepi64_epi8, _mm_cvtusepi64_epi8, _mm256_cvtusepi64_epi8,
	_mm_cvtepi64_epi16, _mm256_cvtepi64_epi16, _mm_cvtsepi64_epi16,
	_mm256_cvtsepi64_epi16, _mm_cvtusepi64_epi16, _mm256_cvtusepi64_epi16,
	_mm_cvtepi64_epi32, _mm256_cvtepi64_epi32, _mm_cvtsepi64_epi32,
	_mm256_cvtsepi64_epi32, _mm_cvtusepi64_epi32, _mm256_cvtusepi64_epi32,
	_mm_maskz_set1_epi32, _mm_maskz_set1_epi64): Formatting fixes.
	(_mm_maskz_cvtps_ph, _mm256_maskz_cvtps_ph): Use _mm_setzero_si128
	instead of _mm_setzero_hi.
	(_mm256_permutex_pd, _mm256_maskz_permutex_epi64, _mm256_insertf32x4,
	_mm256_maskz_insertf32x4, _mm256_inserti32x4, _mm256_maskz_inserti32x4,
	_mm256_extractf32x4_ps, _mm256_maskz_extractf32x4_ps,
	_mm256_shuffle_i32x4, _mm256_maskz_shuffle_i32x4, _mm256_shuffle_f64x2,
	_mm256_maskz_shuffle_f64x2, _mm256_shuffle_f32x4,
	_mm256_maskz_shuffle_f32x4, _mm256_maskz_shuffle_pd,
	_mm_maskz_shuffle_pd, _mm256_maskz_shuffle_ps, _mm_maskz_shuffle_ps,
	_mm256_maskz_srli_epi32, _mm_maskz_srli_epi32, _mm_maskz_srli_epi64,
	_mm256_mask_slli_epi32, _mm256_maskz_slli_epi32, _mm256_mask_slli_epi64,
	_mm256_maskz_slli_epi64, _mm256_roundscale_ps,
	_mm256_maskz_roundscale_ps, _mm256_roundscale_pd,
	_mm256_maskz_roundscale_pd, _mm_roundscale_ps, _mm_maskz_roundscale_ps,
	_mm_roundscale_pd, _mm_maskz_roundscale_pd, _mm256_getmant_ps,
	_mm256_maskz_getmant_ps, _mm_getmant_ps, _mm_maskz_getmant_ps,
	_mm256_getmant_pd, _mm256_maskz_getmant_pd, _mm_getmant_pd,
	_mm_maskz_getmant_pd, _mm256_maskz_shuffle_epi32,
	_mm_maskz_shuffle_epi32, _mm256_rol_epi32, _mm256_maskz_rol_epi32,
	_mm_rol_epi32, _mm_maskz_rol_epi32, _mm256_ror_epi32,
	_mm256_maskz_ror_epi32, _mm_ror_epi32, _mm_maskz_ror_epi32,
	_mm_maskz_alignr_epi32, _mm_maskz_alignr_epi64,
	_mm256_maskz_srai_epi32, _mm_maskz_srai_epi32, _mm_srai_epi64,
	_mm_maskz_srai_epi64, _mm256_maskz_permutex_pd,
	_mm256_maskz_permute_pd, _mm256_maskz_permute_ps, _mm_maskz_permute_pd,
	_mm_maskz_permute_ps, _mm256_permutexvar_ps): Formatting fixes.
	(_mm_maskz_slli_epi64, _mm_rol_epi64, _mm_maskz_rol_epi64,
	_mm_ror_epi64, _mm_maskz_ror_epi64): Use _mm_setzero_si128 instead of
	_mm_setzero_di.
	(_mm_maskz_cvtps_ph, _mm256_maskz_cvtps_ph): Use _mm_setzero_si128
	instead of _mm_setzero_hi.
	* config/i386/avx512dqintrin.h (_mm512_broadcast_f64x2,
	_mm512_broadcast_i64x2, _mm512_broadcast_f32x2, _mm512_broadcast_i32x2,
	_mm512_broadcast_f32x8, _mm512_broadcast_i32x8): Formatting fixes.
	(_mm512_extracti64x2_epi64, _mm512_maskz_extracti64x2_epi64): Use
	_mm_setzero_si128 instead of _mm_setzero_di.
	(_mm512_cvtt_roundpd_epi64, _mm512_mask_cvtt_roundpd_epi64,
	_mm512_maskz_cvtt_roundpd_epi64, _mm512_cvtt_roundpd_epu64,
	_mm512_mask_cvtt_roundpd_epu64, _mm512_maskz_cvtt_roundpd_epu64,
	_mm512_cvtt_roundps_epi64, _mm512_mask_cvtt_roundps_epi64,
	_mm512_maskz_cvtt_roundps_epi64, _mm512_cvtt_roundps_epu64,
	_mm512_mask_cvtt_roundps_epu64, _mm512_maskz_cvtt_roundps_epu64,
	_mm512_cvt_roundpd_epi64, _mm512_mask_cvt_roundpd_epi64,
	_mm512_maskz_cvt_roundpd_epi64, _mm512_cvt_roundpd_epu64,
	_mm512_mask_cvt_roundpd_epu64, _mm512_maskz_cvt_roundpd_epu64,
	_mm512_cvt_roundps_epi64, _mm512_mask_cvt_roundps_epi64,
	_mm512_maskz_cvt_roundps_epi64, _mm512_cvt_roundps_epu64,
	_mm512_mask_cvt_roundps_epu64, _mm512_maskz_cvt_roundps_epu64,
	_mm512_cvt_roundepi64_ps, _mm512_mask_cvt_roundepi64_ps,
	_mm512_maskz_cvt_roundepi64_ps, _mm512_cvt_roundepu64_ps,
	_mm512_mask_cvt_roundepu64_ps, _mm512_maskz_cvt_roundepu64_ps,
	_mm512_cvt_roundepi64_pd, _mm512_mask_cvt_roundepi64_pd,
	_mm512_maskz_cvt_roundepi64_pd, _mm512_cvt_roundepu64_pd,
	_mm512_mask_cvt_roundepu64_pd, _mm512_maskz_cvt_roundepu64_pd,
	_mm512_reduce_pd, _mm512_maskz_reduce_pd, _mm512_reduce_ps,
	_mm512_maskz_reduce_ps, _mm512_extractf32x8_ps,
	_mm512_maskz_extractf32x8_ps, _mm512_extractf64x2_pd,
	_mm512_maskz_extractf64x2_pd, _mm512_extracti32x8_epi32,
	_mm512_maskz_extracti32x8_epi32, _mm512_range_pd,
	_mm512_maskz_range_pd, _mm512_range_ps, _mm512_maskz_range_ps,
	_mm512_range_round_pd, _mm512_maskz_range_round_pd,
	_mm512_range_round_ps, _mm512_maskz_range_round_ps,
	_mm512_maskz_insertf64x2, _mm512_insertf32x8,
	_mm512_maskz_insertf32x8): Formatting fixes.
	(_mm512_extracti64x2_epi64, _mm512_maskz_extracti64x2_epi64): Use
	_mm_setzero_si128 instead of _mm_setzero_di.
	* config/i386/avx512vldqintrin.h (_mm_cvttpd_epi64,
	_mm_cvttpd_epu64, _mm_cvtpd_epi64, _mm_cvtpd_epu64,
	_mm_cvttps_epi64, _mm_maskz_cvttps_epi64, _mm_cvttps_epu64,
	_mm_maskz_cvttps_epu64, _mm_maskz_mullo_epi64, _mm_cvtps_epi64,
	_mm_maskz_cvtps_epi64, _mm_cvtps_epu64, _mm_maskz_cvtps_epu64,
	_mm256_extracti64x2_epi64, _mm256_maskz_extracti64x2_epi64): Use
	_mm_setzero_si128 instead of _mm_setzero_di.
	(_mm256_extracti64x2_epi64, _mm256_maskz_extracti64x2_epi64):
	Likewise in macros.
	* config/i386/avx512vlbwintrin.h (_mm_maskz_mov_epi8,
	_mm_maskz_loadu_epi16, _mm_maskz_mov_epi16, _mm_maskz_loadu_epi8,
	_mm_permutexvar_epi16, _mm_maskz_maddubs_epi16): Use
	_mm_setzero_si128 instead of _mm_setzero_hi.
	(_mm_maskz_min_epu16, _mm_maskz_max_epu8, _mm_maskz_max_epi8,
	_mm_maskz_min_epu8, _mm_maskz_min_epi8, _mm_maskz_max_epi16,
	_mm_maskz_max_epu16, _mm_maskz_min_epi16): Use _mm_setzero_si128
	instead of _mm_setzero_di.
	(_mm_dbsad_epu8, _mm_maskz_shufflehi_epi16,
	_mm_maskz_shufflelo_epi16): Use _mm_setzero_si128 instead of
	_mm_setzero_hi.
	(_mm_maskz_shufflehi_epi16, _mm_maskz_shufflelo_epi16,
	_mm_maskz_slli_epi16): Use _mm_setzero_si128 instead of
	_mm_setzero_hi.
	(_mm_maskz_alignr_epi8): Use _mm_setzero_si128 instead of
	_mm_setzero_di.
	(_mm_maskz_mulhi_epi16, _mm_maskz_mulhi_epu16, _mm_maskz_mulhrs_epi16,
	_mm_maskz_mullo_epi16, _mm_srav_epi16, _mm_srlv_epi16,
	_mm_sllv_epi16): Use _mm_setzero_si128 instead of _mm_setzero_hi.

From-SVN: r242707

gcc/ChangeLog:

2016-11-21  Carl Love  <cel@us.ibm.com>

        * config/rs6000/rs6000-c.c: Add built-in support for vector compare
        equal and vector compare not equal.  The vector compares take two
        arguments of type vector bool char, vector bool short, vector bool int,
        vector bool long long with the same return type.
        * doc/extend.texi: Update built-in documentation file for the new
        powerpc built-ins.

gcc/testsuite/ChangeLog:

2016-11-21  Carl Love  <cel@us.ibm.com>

        * gcc.target/powerpc/builtins-3.c: New file to test the new
        built-ins for vector compare equal and vector compare not equal.

From-SVN: r242706

gcc/ChangeLog

	* Makefile.in ($(lang_checks_parallelized)): Fix detection
	of -j argument.

gcc/ada/ChangeLog

	* gcc-interface/Make-lang.in (check-acats): Fix detection
	of -j argument.

libstdc++-v3/ChangeLog

	* testsuite/Makefile.am
	(check-DEJAGNU $(check_DEJAGNU_normal_targets)): Fix detection
	of -j argument.
	* testsuite/Makefile.in: Regenereate.

From-SVN: r242705

	PR libstdc++/78465
	* testsuite/29_atomics/headers/atomic/macros.cc: Replace runtime tests
	with preprocessor conditions.

From-SVN: r242704

2016-11-22  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/78443
	* class.c (add_proc_comp): Add a vtype component for non-overridable
	procedures that are overriding.

2016-11-22  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/78443
	* gfortran.dg/typebound_proc_35.f90: New test case.

From-SVN: r242703

gcc/testsuite/
	* gcc.c-torture/execute/pr30778.c (memset): Use size_t for 3rd
	parameter in declaration.

From-SVN: r242702

gcc/testsuite/
	* gcc.dg/loop-split.c: Require int32plus.
	* gcc.dg/stack-layout-dynamic-1.c: Require ptr32plus.

From-SVN: r242701

2016-11-22  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        * gcc.target/arm/pr53447-5.c: Fix test expectations for neon-fpu.

From-SVN: r242700

gcc/testsuite/
	* c-c++-common/builtin-shuffle-1.c (V): Use 4 * int in vector.

From-SVN: r242697

2016-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config.gcc: Allow new rmprofile value for configure option
    --with-multilib-list.
    * config/arm/t-rmprofile: New file.
    * doc/install.texi (--with-multilib-list): Document new rmprofile value
    for ARM.

From-SVN: r242696

	PR target/78439
	* config/arm/vfp.md (*movdi_vfp_cortexa8): Use 'q' constraints for the
	register operand in alternatives 4,5,6.

	* gcc.c-torture/compile/pr78439.c: New test.

From-SVN: r242695

re PR target/77904 ([ARM Cortex-M0] Frame pointer thrashes registers if assembly statements with "sp" clobber are used)

2016-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/77904
    * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer
    in save register mask if it is needed.

    gcc/testsuite/
    PR target/77904
    * gcc.target/arm/pr77904.c: New test.

From-SVN: r242693

gcc/testsuite/

	* gcc.target/mips/interrupt_handler-bug-1.c (dg-options): Add
	isa_rev>=2.

From-SVN: r242692

	PR tree-optimization/78436
	* gimple-ssa-store-merging.c (zero_char_buf): Removed.
	(shift_bytes_in_array, shift_bytes_in_array_right,
	merged_store_group::apply_stores): Formatting fixes.
	(clear_bit_region): Likewise.  Use memset.
	(encode_tree_to_bitpos): Formatting fixes.  Fix comment typos - EPXR
	instead of EXPR and inerted instead of inserted.  Use memset instead
	of zero_char_buf.  For !BYTES_BIG_ENDIAN decrease byte_size by 1
	if shift_amnt is 0.

	* gcc.c-torture/execute/pr78436.c: New test.

From-SVN: r242691

	PR middle-end/78416
	* expmed.c (expand_divmod): Use wide_int for computation of
	op1_is_pow2.  Don't set it if op1 is 0.  Formatting fixes.
	Use size <= HOST_BITS_PER_WIDE_INT instead of
	HOST_BITS_PER_WIDE_INT >= size.

	* gcc.dg/torture/pr78416.c: New test.

From-SVN: r242690

	PR tree-optimization/78445
	* tree-if-conv.c (tree_if_conversion): If any_pred_load_store or
	any_complicated_phi, version loop even if flag_tree_loop_if_convert is
	1.  Formatting fix.

	* gcc.dg/pr78445.c: New test.

From-SVN: r242689

ARM and AArch64 may not support trapping so runtime and
compile time check can differ.

gcc/testsuite/
	PR libgfortran/78449 
	* gfortran.dg/ieee/ieee_8.f90 (aarch64*gnu, arm*gnu*): Mark xfail.

From-SVN: r242688

	PR ipa/78309
	* ipa-icf.c (void sem_item::set_hash): Update m_hash_set.
	(sem_function::get_hash): Use the new field.
	(sem_function::parse): Remove an argument from ctor.
	(sem_variable::parse): Likewise.
	(sem_variable::get_hash): Use the new field.
	(sem_item_optimizer::read_section): Use new ctor and set hash.
	* ipa-icf.h: _hash is removed from sem_item::sem_item,
	sem_variable::sem_variable, sem_function::sem_function.

From-SVN: r242687

From-SVN: r242686

re PR target/68538 (ICE in gen_reg_rtx, at emit-rtl.c:1027 when cross-compiling for cris-linux-gnu target)

	PR target/68538
	* config/cris/cris.md: Don't call copy_to_mode_reg unless
	can_create_pseudo_p is true.

        PR target/68538
	* gcc.c-torture/compile/pr68538.c: New test.

From-SVN: r242682

We didn't have patterns yet for rl[wd]imi insns that do a rotate by 0.
This fixes it.


	PR target/68803
	* config/rs6000/rs6000.md (*rotlsi3_insert_5, *rotldi3_insert_6,
	*rotldi3_insert_7): New define_insns.

From-SVN: r242681

rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated to FP/vector registers in...

[gcc]
2016-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (movdi_internal32): Change constraints
	so that DImode can be allocated to FP/vector registers in more
	cases, and we can avoid direct move operations.  If the register
	needs reloading, prefer GPRs over FP/vector registers.  In the
	case of FPR vs. Altivec registers, prefer FPR registers unless we
	have the ISA 3.0 reg+offset scalar instructions.
	(movdi_internal64): Likewise.

[gcc/testsuite]
2016-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS
	to be generated instead of FCTIWUZ or FCTIWZ.

From-SVN: r242679

	PR middle-end/67335
	* omp-simd-clone.c (simd_clone_adjust_argument_types): Use NULL prefix
	for tmp simd array if DECL_NAME (parm) is NULL.

	* g++.dg/vect/simd-clone-7.cc: New test.

From-SVN: r242678

	PR c++/71973
	* g++.dg/torture/pr53321.C (size_t): Use __SIZE_TYPE__ instead of
	long unsigned int.
	* g++.dg/torture/pr63512.C (::strlen): Use __SIZE_TYPE__ instead of
	unsigned long.

From-SVN: r242677

	PR target/25128
	* config/m68k/predicates.md (swap_peephole_relational_operator): New
	predicate.
	* config/m68k/m68k.md (relational tests against 65535/65536): New
	peephole2.

	PR target/25128
	* gcc.target/m68k/pr25128.c: New test.

From-SVN: r242676

	* tree-ssa-loop-prefetch.c: Delete FIXME after the includes.

From-SVN: r242675

gcc/c-family/ChangeLog:

	* c.opt (-fprintf-return-value): Enable by default.

gcc/ChangeLog:

	* doc/invoke.texi (-fprintf-return-value): Document that option
	is enabled by default.

From-SVN: r242674

gcc/
	* config/avr/avr-c.c (avr_register_target_pragmas): Use C++
	for-loop declaration of loop variable.
	(avr_register_target_pragmas, avr_cpu_cpp_builtins): Same.
	* config/avr/avr.c (avr_popcount_each_byte)
	(avr_init_expanders, avr_regs_to_save, sequent_regs_live)
	(get_sequence_length, avr_prologue_setup_frame, avr_map_metric)
	(avr_expand_epilogue, avr_function_arg_advance)
	(avr_out_compare, avr_out_plus_1, avr_out_bitop, avr_out_fract)
	(avr_rotate_bytes, _reg_unused_after, avr_assemble_integer)
	(avr_adjust_reg_alloc_order, output_reload_in_const)
	(avr_conditional_register_usage, avr_find_unused_d_reg)
	(avr_map_decompose, avr_fold_builtin): Same.

From-SVN: r242672

	libstdc++-v3:
	* acinclude.m4 (GLIBCXX_CHECK_MATH11_PROTO): Update comments.
	(__CORRECT_ISO_CPP11_MATH_H_PROTO): Rename to ...
	(__CORRECT_ISO_CPP11_MATH_H_PROTO_FP): ... this.
	Add test for C++11 <math.h> integral overloads.
	* configure: Regenerate.
	* config.h.in: Regenerate.

	* include/c_global/cmath [__cplusplus >= 201103L]: Reflect
	__CORRECT_ISO_CPP11_MATH_H_PROTO to
	__CORRECT_ISO_CPP11_MATH_H_PROTO_FP rename.
	* include/c_global/cmath [_GLIBCXX_USE_C99_MATH &&
	!_GLIBCXX_USE_C99_FP_MACROS_DYNAMIC && __cplusplus >= 201103L]
	(std::fpclassify): Wrap in !__CORRECT_ISO_CPP11_MATH_H_PROTO_INT.
	(std::isfinite): Likewise.
	(std::isinf): Likewise.
	(std::isnan): Likewise.
	(std::isnormal): Likewise.
	(std::signbit): Likewise.
	(std::isgreater): Likewise.
	(std::isgreaterequal): Likewise.
	(std::isless): Likewise.
	(std::islessequal): Likewise.
	(std::islessgreater): Likewise.
	(std::isunordered): Likewise.
	[__cplusplus >= 201103L && _GLIBCXX_USE_C99_MATH_TR1]
	(std::acosh): Likewise.
	(std::asinh): Likewise.
	(std::atanh): Likewise.
	(std::cbrt): Likewise.
	(std::copysign): Likewise.
	(std::erf): Likewise.
	(std::erfc): Likewise.
	(std::exp2): Likewise.
	(std::expm1): Likewise.
	(std::fdim): Likewise.
	(std::fma): Likewise.
	(std::fmax): Likewise.
	(std::fmin): Likewise.
	(std::hypot): Likewise.
	(std::ilogb): Likewise.
	(std::lgamma): Likewise.
	(std::llrint): Likewise.
	(std::llround): Likewise.
	(std::log1p): Likewise.
	(std::log2): Likewise.
	(std::logb): Likewise.
	(std::lrint): Likewise.
	(std::lround): Likewise.
	(std::nearbyint): Likewise.
	(std::nextafter): Likewise.
	(std::nexttoward): Likewise.
	(std::remainder): Likewise.
	(std::remquo): Likewise.
	(std::rint): Likewise.
	(std::round): Likewise.
	(std::scalbln): Likewise.
	(std::scalbn): Likewise.
	(std::tgamma): Likewise.
	(std::trunc): Likewise.
	* include/tr1/cmath [_GLIBCXX_USE_C99_MATH_TR1 && __cplusplus >=
	201103L]: Reflect __CORRECT_ISO_CPP11_MATH_H_PROTO to
	__CORRECT_ISO_CPP11_MATH_H_PROTO_FP rename.

	fixincludes:
	* inclhack.def (solaris_math_12): New fix.
	(hpux11_fabsf): Replace bypass by *-hp-hpux11* mach selector.
	* fixincl.x: Regenerate.
	* tests/base/math.h [SOLARIS_MATH_12_CHECK]: New test.

From-SVN: r242671

gcc/
	* config/avr/avr.c (avr_popcount): Remove static function.
	(avr_popcount_each_byte, avr_out_bitop): Use popcount_hwi instead.

From-SVN: r242670

	* arm.opt (mapcs-float): Delete option
	* arm.c (arm_option_override): Remove hunk relating to
	TARGET_APCS_FLOAT.
	* doc/invoke.texi (arm options): Remove documentation for -mapcs-float.

From-SVN: r242669

We treated this g as a sibling call to f:

      int f (int);
      int g (void) { return f (1); }

but not this one:

      struct s { int i; };
      struct s f (int);
      struct s g (void) { return f (1); }

We treated them both as sibcalls on x86 before the first patch for PR36326,
so I suppose this is a regression of sorts from 4.3.

The patch allows function returns to be local aggregate variables as well
as gimple registers.

gcc/
	* tree-tailcall.c (process_assignment): Simplify the check for
	a valid copy, allowing the source to be a local variable as
	well as an SSA name.
	(find_tail_calls): Allow copies between local variables to follow
	the call.  Allow the result to be stored in any local variable,
	even if it's an aggregate.
	(eliminate_tail_call): Check whether the result is an SSA name
	before updating its SSA_NAME_DEF_STMT.

gcc/testsuite/
	* gcc.dg/tree-ssa/tailcall-7.c: New test.

From-SVN: r242668

gcc/ChangeLog:
	PR preprocessor/78324
	* input.c (get_substring_ranges_for_loc): Fail gracefully if
	-ftrack-macro-expansion has a value other than 2.

gcc/testsuite/ChangeLog:
	PR preprocessor/78324
	* gcc.dg/plugin/diagnostic-test-string-literals-1.c
	(test_multitoken_macro): New function.
	* gcc.dg/plugin/diagnostic-test-string-literals-3.c: New test
	case.
	* gcc.dg/plugin/diagnostic-test-string-literals-4.c: New test
	case.
	* gcc.dg/plugin/plugin.exp (plugin_test_list): Add the new test
	cases.
	* gcc.dg/tree-ssa/builtin-sprintf-warn-1.c (test_sprintf_note):
	Move to...
	* gcc.dg/tree-ssa/builtin-sprintf-warn-4.c: ...here.  Drop
	-ftrack-macro-expansion=0.
	(test_sprintf_note): Remove "P" macro.  Add
	dg-begin/end-multiline-output directives.
	(LINE, buffer, ptr): Copy from builtin-sprintf-warn-1.c.

From-SVN: r242667

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_tiny) [avr]:
	Return 1 for AVR_TINY.

From-SVN: r242666

gcc/testsuite/
	PR rtl-optimization/71785
	* gcc.target/powerpc/pr71785.c: New file.

From-SVN: r242665

	gcc/testsuite
	PR testsuite/78114
	* gfortran.dg/vect/fast-math-mgrid-resid.f: Add additional
	options.  Refine test by checking predictive commining PHI
	nodes in vectorized loop wrto vector factor.

From-SVN: r242664