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Commit d85e598a by Michael Meissner Committed by Michael Meissner
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rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated… 

rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated to FP/vector registers in...

[gcc]
2016-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (movdi_internal32): Change constraints
	so that DImode can be allocated to FP/vector registers in more
	cases, and we can avoid direct move operations.  If the register
	needs reloading, prefer GPRs over FP/vector registers.  In the
	case of FPR vs. Altivec registers, prefer FPR registers unless we
	have the ISA 3.0 reg+offset scalar instructions.
	(movdi_internal64): Likewise.

[gcc/testsuite]
2016-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS
	to be generated instead of FCTIWUZ or FCTIWZ.

From-SVN: r242679
parent 699e8cb7
Showing with 24 additions and 9 deletions
gcc/ChangeLog
2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (movdi_internal32): Change constraints
so that DImode can be allocated to FP/vector registers in more
cases, and we can avoid direct move operations. If the register
needs reloading, prefer GPRs over FP/vector registers. In the
case of FPR vs. Altivec registers, prefer FPR registers unless we
have the ISA 3.0 reg+offset scalar instructions.
(movdi_internal64): Likewise.
2016-11-21 Jakub Jelinek <jakub@redhat.com>
PR middle-end/67335
gcc/config/rs6000/rs6000.md
......@@ -8118,10 +8118,10 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
"=Y, r, r, ?m, ?*d, ?*d,
r, ?wY, ?Z, ?*wb, ?*wv, ?wi,
?wo, ?wo, ?wv, ?wi, ?wi, ?wv,
?wv")
"=Y, r, r, ^m, ^d, ^d,
r, ^wY, $Z, ^wb, $wv, ^wi,
*wo, *wo, *wv, *wi, *wi, *wv,
*wv")
(match_operand:DI 1 "input_operand"
"r, Y, r, d, m, d,
......@@ -8195,9 +8195,9 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, r, r, r,
?m, ?*d, ?*d, ?wY, ?Z, ?*wb,
?*wv, ?wi, ?wo, ?wo, ?wv, ?wi,
?wi, ?wv, ?wv, r, *h, *h,
^m, ^d, ^d, ^Y, $Z, $wb,
$wv, ^wi, *wo, *wo, *wv, *wi,
*wi, *wv, *wv, r, *h, *h,
?*r, ?*wg, ?*r, ?*wj")
(match_operand:DI 1 "input_operand"
......
gcc/testsuite/ChangeLog
2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS
to be generated instead of FCTIWUZ or FCTIWZ.
2016-11-21 Jakub Jelinek <jakub@redhat.com>
PR middle-end/67335
......
gcc/testsuite/gcc.target/powerpc/ppc-round2.c
......@@ -5,8 +5,8 @@
/* { dg-options "-O2 -mcpu=power8" } */
/* { dg-final { scan-assembler-times "fcfid " 2 } } */
/* { dg-final { scan-assembler-times "fcfids " 2 } } */
/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
/* { dg-final { scan-assembler-times "fctiwuz \|xscvdpuxws " 2 } } */
/* { dg-final { scan-assembler-times "fctiwz \|xscvdpsxws " 2 } } */
/* { dg-final { scan-assembler-times "mfvsrd " 4 } } */
/* { dg-final { scan-assembler-times "mtvsrwa " 2 } } */
/* { dg-final { scan-assembler-times "mtvsrwz " 2 } } */
......
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