This adds weak linkage to internal TypeInfo data on top of the existing
DECL_COMDAT, which helps in the unlikely event that two of the same
TypeInfo data ends up in multiple places.

gcc/d/ChangeLog:

	* typeinfo.cc (TypeInfoVisitor::internal_reference): Call
	d_comdat_linkage on generated decl.

Replace all relevant explicit uses of V64 vectors with an iterator (albeit
with only one entry).  This is prerequisite to adding extra vector lengths.

The changes are purely mechanical: comparing the mddump files from before
and after shows only white-space differences and the use of GET_MODE_NUNITS.

2020-03-31  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
	New mode iterators.
	(vnsi, VnSI, vndi, VnDI): New mode attributes.
	(mov<mode>): Use <VnDI> in place of V64DI.
	(mov<mode>_exec): Likewise.
	(mov<mode>_sgprbase): Likewise.
	(reload_out<mode>): Likewise.
	(*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
	(gather_load<mode>v64si): Rename to ...
	(gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
	and <VnDI> in place of V64DI.
	(gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
	(gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
	(gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
	(scatter_store<mode>v64si): Rename to ...
	(scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
	(scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
	(scatter<mode>_insn_1offset<exec_scatter>): Likewise.
	(scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
	(scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
	(ds_bpermute<mode>): Use <VnSI>.
	(addv64si3_vcc<exec_vcc>): Rename to ...
	(add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
	(addv64si3_vcc_dup<exec_vcc>): Rename to ...
	(add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
	(addcv64si3<exec_vcc>): Rename to ...
	(addc<mode>3<exec_vcc>): ... this, and use V_SI.
	(subv64si3_vcc<exec_vcc>): Rename to ...
	(sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
	(subcv64si3<exec_vcc>): Rename to ...
	(subc<mode>3<exec_vcc>): ... this, and use V_SI.
	(addv64di3): Rename to ...
	(add<mode>3): ... this, and use V_DI.
	(addv64di3_exec): Rename to ...
	(add<mode>3_exec): ... this, and use V_DI.
	(subv64di3): Rename to ...
	(sub<mode>3): ... this, and use V_DI.
	(subv64di3_exec): Rename to ...
	(sub<mode>3_exec): ... this, and use V_DI.
	(addv64di3_zext): Rename to ...
	(add<mode>3_zext): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_exec): Rename to ...
	(add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup): Rename to ...
	(add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup_exec): Rename to ...
	(add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup2): Rename to ...
	(add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup2_exec): Rename to ...
	(add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
	(addv64di3_sext_dup2): Rename to ...
	(add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
	(addv64di3_sext_dup2_exec): Rename to ...
	(add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
	(<su>mulv64si3_highpart<exec>): Rename to ...
	(<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
	(mulv64di3): Rename to ...
	(mul<mode>3): ... this, and use V_DI and <VnSI>.
	(mulv64di3_exec): Rename to ...
	(mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext): Rename to ...
	(mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext_exec): Rename to ...
	(mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext_dup2): Rename to ...
	(mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext_dup2_exec): Rename to ...
	(mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
	(<expander>v64di3): Rename to ...
	(<expander><mode>3): ... this, and use V_DI and <VnSI>.
	(<expander>v64di3_exec): Rename to ...
	(<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
	(<expander>v64si3<exec>): Rename to ...
	(<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
	(v<expander>v64si3<exec>): Rename to ...
	(v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
	(<expander>v64si3<exec>): Rename to ...
	(<expander><vnsi>3<exec>): ... this, and use V_SI.
	(subv64df3<exec>): Rename to ...
	(sub<mode>3<exec>): ... this, and use V_DF.
	(truncv64di<mode>2): Rename to ...
	(trunc<vndi><mode>2): ... this, and use <VnDI>.
	(truncv64di<mode>2_exec): Rename to ...
	(trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
	(<convop><mode>v64di2): Rename to ...
	(<convop><mode><vndi>2): ... this, and use <VnDI>.
	(<convop><mode>v64di2_exec): Rename to ...
	(<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
	(vec_cmp<u>v64qidi): Rename to ...
	(vec_cmp<u><mode>di): ... this, and use <VnSI>.
	(vec_cmp<u>v64qidi_exec): Rename to ...
	(vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
	(vcond_mask_<mode>di): Use <VnDI>.
	(maskload<mode>di): Likewise.
	(maskstore<mode>di): Likewise.
	(mask_gather_load<mode>v64si): Rename to ...
	(mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
	(mask_scatter_store<mode>v64si): Rename to ...
	(mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
	(*<reduc_op>_dpp_shr_v64di): Rename to ...
	(*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
	(*plus_carry_in_dpp_shr_v64si): Rename to ...
	(*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
	(*plus_carry_dpp_shr_v64di): Rename to ...
	(*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
	(vec_seriesv64si): Rename to ...
	(vec_series<mode>): ... this, and use V_SI.
	(vec_seriesv64di): Rename to ...
	(vec_series<mode>): ... this, and use V_DI.

Use HOST_WIDE_INT_PRINT_DEC macro instead of %ld for format printing.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_print_operand): Use
	HOST_WIDE_INT_PRINT_DEC macro.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.

For the following MVE ACLE intrinsics, polymorphic variant support is missing on the trunk.

vbicq_n_s16, vbicq_n_s32, vbicq_n_u16 and vbicq_n_u32.

This patch add the polymorphic variant support for above intrinsics.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
	variant.
	(__arm_vbicq): Likewise.

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.

Enable big-endian suffixed dynamic linker per glibc multi-abi support.

And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.

gcc/
xxxx-xx-xx  Vineet Gupta <vgupta@synopsys.com>

       * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700

For the following MVE ACLE intrinsics, polymorphic variant supports only +mve option, support for +mve.fp is missing.

vabavq_p_s16, vabavq_p_s32, vabavq_p_s8, vabavq_p_u16, vabavq_p_u32, vabavq_p_u8, vabavq_s16, vabavq_s32, vabavq_s8, vabavq_u16, vabavq_u32, vabavq_u8, vaddlvaq_p_s32, vaddlvaq_p_u32, vaddlvaq_s32, vaddlvaq_u32, vaddlvq_p_s32, vaddlvq_p_u32, vaddlvq_u32, vaddvaq_p_s16, vaddvaq_p_s32, vaddvaq_p_s8, vaddvaq_p_u16, vaddvaq_p_u32, vaddvaq_p_u8, vaddvaq_s16, vaddvaq_s32, vaddvaq_s8, vaddvaq_u16, vaddvaq_u32, vaddvaq_u8, vaddvq_p_s16, vaddvq_p_s32, vaddvq_p_s8, vaddvq_p_u16, vaddvq_p_u32, vaddvq_p_u8, vaddvq_s8, vaddvq_u16, vaddvq_u32, vaddvq_u8, vcmpcsq_m_n_u16, vcmpcsq_m_n_u32, vcmpcsq_m_n_u8, vcmpcsq_m_u16, vcmpcsq_m_u32, vcmpcsq_m_u8, vcmpcsq_n_u16, vcmpcsq_n_u32, vcmpcsq_n_u8, vcmpcsq_u16, vcmpcsq_u32, vcmpcsq_u8, vcmpeqq_n_f16, vcmpeqq_n_f32, vcmpgeq_m_n_s16, vcmpgeq_m_n_s32, vcmpgeq_m_n_s8, vcmpgtq_m_n_f16, vcmpgtq_m_n_f32, vcmpgtq_n_f16, vcmpgtq_n_f32, vcmphiq_m_n_u16, vcmphiq_m_n_u32, vcmphiq_m_n_u8, vcmphiq_m_u16, vcmphiq_m_u32, vcmphiq_m_u8, vcmphiq_n_u16, vcmphiq_n_u32, vcmphiq_n_u8, vcmphiq_u16, vcmphiq_u32, vcmphiq_u8, vcmpleq_m_n_f16, vcmpleq_m_n_f32, vcmpleq_n_f16, vcmpleq_n_f32, vcmpltq_m_n_f16, vcmpltq_m_n_f32, vcmpneq_m_n_f16, vcmpneq_m_n_f32, vcmpneq_n_f16, vcmpneq_n_f32, vmaxavq_p_s16, vmaxavq_p_s32, vmaxavq_p_s8, vmaxavq_s16, vmaxavq_s32, vmaxavq_s8, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8, vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vmaxvq_p_s16, vmaxvq_p_s32, vmaxvq_p_s8, vmaxvq_p_u16, vmaxvq_p_u32, vmaxvq_p_u8, vmaxvq_s16, vmaxvq_s32, vmaxvq_s8, vmaxvq_u16, vmaxvq_u32, vmaxvq_u8, vminavq_p_s16, vminavq_p_s32, vminavq_p_s8, vminavq_s16, vminavq_s32, vminavq_s8, vminq_x_s16, vminq_x_s32, vminq_x_s8, vminq_x_u16, vminq_x_u32, vminq_x_u8, vminvq_p_s16, vminvq_p_s32, vminvq_p_s8, vminvq_p_u16, vminvq_p_u32, vminvq_p_u8, vminvq_s16, vminvq_s32, vminvq_s8, vminvq_u16, vminvq_u32, vminvq_u8, vmladavaq_p_s16, vmladavaq_p_s32, vmladavaq_p_s8, vmladavaq_p_u16, vmladavaq_p_u32, vmladavaq_p_u8, vmladavaq_s16, vmladavaq_s32, vmladavaq_s8, vmladavaq_u16, vmladavaq_u32, vmladavaq_u8, vmladavaxq_s16, vmladavaxq_s32, vmladavaxq_s8, vmladavq_p_s16, vmladavq_p_s32, vmladavq_p_s8, vmladavq_p_u16, vmladavq_p_u32, vmladavq_p_u8, vmladavq_s16, vmladavq_s32, vmladavq_s8, vmladavq_u16, vmladavq_u32, vmladavq_u8, vmladavxq_p_s16, vmladavxq_p_s32, vmladavxq_p_s8, vmladavxq_s16, vmladavxq_s32, vmladavxq_s8, vmlaldavaq_s16, vmlaldavaq_s32, vmlaldavaq_u16, vmlaldavaq_u32, vmlaldavaxq_s16, vmlaldavaxq_s32, vmlaldavq_p_s16, vmlaldavq_p_s32, vmlaldavq_p_u16, vmlaldavq_p_u32, vmlaldavq_s16, vmlaldavq_s32, vmlaldavq_u16, vmlaldavq_u32, vmlaldavxq_p_s16, vmlaldavxq_p_s32, vmlsdavaq_s16, vmlsdavaq_s32, vmlsdavaq_s8, vmlsdavaxq_s16, vmlsdavaxq_s32, vmlsdavaxq_s8, vmlsdavq_p_s16, vmlsdavq_p_s32, vmlsdavq_p_s8, vmlsdavq_s16, vmlsdavq_s32, vmlsdavq_s8, vmlsdavxq_p_s16, vmlsdavxq_p_s32, vmlsdavxq_p_s8, vmlsdavxq_s16, vmlsdavxq_s32, vmlsdavxq_s8, vmlsldavaq_s16, vmlsldavaq_s32, vmlsldavaxq_s16, vmlsldavaxq_s32, vmlsldavq_p_s16, vmlsldavq_p_s32, vmlsldavq_s16, vmlsldavq_s32, vmlsldavxq_p_s16, vmlsldavxq_p_s32, vmlsldavxq_s16, vmlsldavxq_s32, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8, vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8, vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8, vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8, vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32, vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vrmlaldavhaxq_s32, vrmlaldavhq_p_s32, vrmlaldavhq_p_u32, vrmlaldavhq_s32, vrmlaldavhq_u32, vrmlaldavhxq_p_s32, vrmlaldavhxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vrmlsldavhq_p_s32, vrmlsldavhq_s32, vrmlsldavhxq_p_s32, vrmlsldavhxq_s32, vstrbq_p_s16, vstrbq_p_s32, vstrbq_p_s8, vstrbq_p_u16, vstrbq_p_u32, vstrbq_p_u8, vstrbq_s16, vstrbq_s32, vstrbq_s8, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_u16, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s8, vstrbq_scatter_offset_u16, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u8, vstrbq_u16, vstrbq_u32, vstrbq_u8, vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64,
vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64,
vstrdq_scatter_shifted_offset_u64.

This patch adds the support for MVE ACLE intrinsics polymorphic variants with +mve.fp option.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
	common section of both MVE Integer and MVE Floating Point.
	(vaddvq): Likewise.
	(vaddlvq_p): Likewise.
	(vaddvaq): Likewise.
	(vaddvq_p): Likewise.
	(vcmpcsq): Likewise.
	(vmlsdavxq): Likewise.
	(vmlsdavq): Likewise.
	(vmladavxq): Likewise.
	(vmladavq): Likewise.
	(vminvq): Likewise.
	(vminavq): Likewise.
	(vmaxvq): Likewise.
	(vmaxavq): Likewise.
	(vmlaldavq): Likewise.
	(vcmphiq): Likewise.
	(vaddlvaq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavq): Likewise.
	(vabavq): Likewise.
	(vrmlaldavhaq): Likewise.
	(vcmpgeq_m_n): Likewise.
	(vmlsdavxq_p): Likewise.
	(vmlsdavq_p): Likewise.
	(vmlsdavaxq): Likewise.
	(vmlsdavaq): Likewise.
	(vaddvaq_p): Likewise.
	(vcmpcsq_m_n): Likewise.
	(vcmpcsq_m): Likewise.
	(vmladavxq_p): Likewise.
	(vmladavq_p): Likewise.
	(vmladavaxq): Likewise.
	(vmladavaq): Likewise.
	(vminvq_p): Likewise.
	(vminavq_p): Likewise.
	(vmaxvq_p): Likewise.
	(vmaxavq_p): Likewise.
	(vcmphiq_m): Likewise.
	(vaddlvaq_p): Likewise.
	(vmlaldavaq): Likewise.
	(vmlaldavaxq): Likewise.
	(vmlaldavq_p): Likewise.
	(vmlaldavxq_p): Likewise.
	(vmlsldavaq): Likewise.
	(vmlsldavaxq): Likewise.
	(vmlsldavq_p): Likewise.
	(vmlsldavxq_p): Likewise.
	(vrmlaldavhaxq): Likewise.
	(vrmlaldavhq_p): Likewise.
	(vrmlaldavhxq_p): Likewise.
	(vrmlsldavhaq): Likewise.
	(vrmlsldavhaxq): Likewise.
	(vrmlsldavhq_p): Likewise.
	(vrmlsldavhxq_p): Likewise.
	(vabavq_p): Likewise.
	(vmladavaq_p): Likewise.
	(vstrbq_scatter_offset): Likewise.
	(vstrbq_p): Likewise.
	(vstrbq_scatter_offset_p): Likewise.
	(vstrdq_scatter_base_p): Likewise.
	(vstrdq_scatter_base): Likewise.
	(vstrdq_scatter_offset_p): Likewise.
	(vstrdq_scatter_offset): Likewise.
	(vstrdq_scatter_shifted_offset_p): Likewise.
	(vstrdq_scatter_shifted_offset): Likewise.
	(vmaxq_x): Likewise.
	(vminq_x): Likewise.
	(vmovlbq_x): Likewise.
	(vmovltq_x): Likewise.
	(vmulhq_x): Likewise.
	(vmullbq_int_x): Likewise.
	(vmullbq_poly_x): Likewise.
	(vmulltq_int_x): Likewise.
	(vmulltq_poly_x): Likewise.
	(vstrbq): Likewise.

gcc/testsuite/ChangeLog:

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.

The following testcase ICEs in final_scan_insn_1.  The problem is in the
@aarch64_compare_and_swaphi define_insn_and_split, since 9 it uses
aarch64_plushi_operand predicate for the "expected value" operand, which
allows either 0..0xfff constants or 0x1000..0xf000 constants (i.e. HImode
values which when zero extended are either 0..0xfff or (0..0xfff) << 12).
The problem is that RA doesn't care about predicates, it honors just
constraints and the used constraint on the operand is n, which means any
HImode CONST_SCALAR_INT.  In the testcase LRA thus propagates the -1
value into the insn.
This is a define_insn_and_split which requires mandatory split.
But during split2 pass, we check the predicate (and don't check
constraints), which fails and thus we don't split it and during final ICE
because the mandatory splitting didn't happen.

The following patch fixes it by adding a matching constraint to the
predicate and using it.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR target/94368
	* config/aarch64/constraints.md (Uph): New constraint.
	* config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
	(@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
	constraint.

	* gcc.dg/pr94368.c: New test.

The following testcase is miscompiled since 4.9, we treat unsigned
vector types as if they were signed and "optimize" negations across it.

2020-03-31  Marc Glisse  <marc.glisse@inria.fr>
	    Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94412
	* fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
	ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.

	* gcc.c-torture/execute/pr94412.c: New test.

Co-authored-by: Marc Glisse <marc.glisse@inria.fr>

The following testcase is optimized with char/unsigned char/signed char,
but not with std::byte.  The following patch fixes that.  Didn't use
INTEGRAL_TYPE_P because bswapping bools is just too weird.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94403
	* gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
	ENUMERAL_TYPE lhs_type.

	* g++.dg/tree-ssa/pr94403.C: New test.

The following patch adjusts simplify_rotate to recognize more rotates,
basically we allow even some same precision integral -> integral
conversions, with the requirement that the RSHIFT_EXPR operand has to be
done in unsigned type (i.e. logical right shift), so that we compensate for
the combiner no longer being able to simplify those into rotates on some
targets.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/94344
	* tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
	conversions, either on both operands of |^+ or just one.  Handle
	also extra same precision conversion on RSHIFT_EXPR first operand
	provided RSHIFT_EXPR is performed in unsigned type.

	* gcc.dg/pr94344.c: New test.

libgccjit's test-threads.c repeatedly compiles and runs numerous tests,
each in a separate thread.

Attempting to add an empty test that generates no code leads to a
double-free ICE within that thread, within lra.c's
finish_insn_code_data_once.

The root cause is that the insn_code_data array is cleared in
init_insn_code_data_once, but this is only called the first time
a cgraph_node is expanded [1], whereas the "loop-over-all-elements
and free them" is unconditionally called in finalize [2].  Hence
if there are no functions:
* the array is not re-initialized for the empty context
* when finish_insn_code_data_once is called for the empty context
it still contains the freed pointers from the previous context
that held the jit mutex, and hence the free is a double-free.

This patch sets the pointers to NULL after freeing them, fixing
the ICE.

[1]
init_insn_code_data_once is called via
  lra_init_once called by
    ira_init_once called by
      initialize_rtl, via:
         if (!rtl_initialized)
           ira_init_once ();
        called by init_function_start
           called by cgraph_node::expand

[2]:
finish_insn_code_data_once is called by:
  lra_finish_once called by
    finalize

gcc/ChangeLog:
	* lra.c (finish_insn_code_data_once): Set the array elements
	to NULL after freeing them.

gcc/testsuite/ChangeLog:
	* jit.dg/all-non-failing-tests.h: Add test-empty.c

	* sv.po: Update.

The resolution of CWG issue 1321 clarified that when deciding whether two
expressions involving template parameters are equivalent, two dependent
function calls where the function is named with an unqualified-id are
considered to be equivalent if the name is the same, even if unqualified
lookup finds different sets of functions.  We were wrongly treating
qualified-ids the same way, so that EXISTS and test::EXISTS were considered
to be equivalent even though they are looking up the name in different
scopes.  This also causes a mangling bug, but I don't think it's safe to fix
that for GCC 10; this patch just fixes the comparison.

gcc/cp/ChangeLog
2020-03-30  Jason Merrill  <jason@redhat.com>

	PR c++/90711
	* tree.c (cp_tree_equal) [CALL_EXPR]: Compare KOENIG_LOOKUP_P.
	(called_fns_equal): Check DECL_CONTEXT.

The following testcase ICEs, because the FE when processing the statement
expression changes the .VEC_CONVERT internal fn CALL_EXPR into .PHI call.
That is because the internal fn call is recorded in the base.u.ifn
field, which overlaps base.u.bits.lang_flag_1 which is used for
STMT_IS_FULL_EXPR_P, so this essentially does ifn |= 2 on little-endian.
STMT_IS_FULL_EXPR_P bit is used in:
cp-gimplify.c-  if (STATEMENT_CODE_P (code))
cp-gimplify.c-    {
cp-gimplify.c-      saved_stmts_are_full_exprs_p = stmts_are_full_exprs_p ();
cp-gimplify.c-      current_stmt_tree ()->stmts_are_full_exprs_p
cp-gimplify.c:        = STMT_IS_FULL_EXPR_P (*expr_p);
cp-gimplify.c-    }
and
pt.c-  if (STATEMENT_CODE_P (TREE_CODE (t)))
pt.c:    current_stmt_tree ()->stmts_are_full_exprs_p = STMT_IS_FULL_EXPR_P (t);
so besides being wrong on some other codes, it actually isn't beneficial at
all to set it on anything else, so the following patch restricts it to
trees with STATEMENT_CODE_P TREE_CODE.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR c++/94385
	* semantics.c (add_stmt): Only set STMT_IS_FULL_EXPR_P on trees with
	STATEMENT_CODE_P code.

	* c-c++-common/pr94385.c: New test.

* config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
Define.

  Disable the code that limits initialization of builtins based
on the rs6000_builtin_mask.  This allows all built-ins to be
properly referenced when building code using #pragma for cpu
targets newer than what was specified by the -mcpu default.
The use of built-ins is still properly limited by logic within
altivec_resolve_overloaded_builtin().

2020-03-30  Will Schmidt  <will_schmidt@vnet.ibm.com>

gcc/
    * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
    to skip defining builtins based on builtin_mask.

gcc/testsuite/
    * gcc.target/powerpc/pragma_power6.c: New.
    * gcc.target/powerpc/pragma_power7.c: New.
    * gcc.target/powerpc/pragma_power8.c: New.
    * gcc.target/powerpc/pragma_power9.c: New.
    * gcc.target/powerpc/pragma_misc9.c: New.
    * gcc.target/powerpc/vsu/vec-all-nez-7.c: Update error message.
    * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Update error message.

Update existing testcase powerpc/bswap64-4.c to
reflect that we generate ldbrx and stdbrx instructions
for newer cpu targets, versus the pair of lwbrx and stwbrx
instructions as seen on previous cpu targets.

2020-03-24  Will Schmidt  <will_schmidt@vnet.ibm.com>

gcc/testsuite/
	* gcc.target/powerpc/bswap64-4.c: Update scan-assembler
	expected results.

This define_insn has two issues.
One is that with -mavx512f -mno-avx512vl it can emit an AVX512VL-only insn
- 128-bit or 256-bit EVEX encoded vpternlog{d,q}.
Another one is that because there is no vpternlog{b,w}, we emit vpternlogd
instead, but then we shouldn't pretend we support masking of that, because
we don't.
The first one can be fixed by forcing the use of %zmm* registers instead of
%xmm* or %ymm* if AVX512F but not AVX512VL, like we do for a couple of other
insns (although that is primarily done in order to support %xmm16+ regs).
But we need to make sure that in that case the input operand isn't memory,
because while we can read and store the higher bits of registers, we don't
want to read from memory more bytes than what we should read.

A variant to these two if_then_else set attrs, condition in the output and
larger condition would be 4 different define_insns (one with something like
VI48_AVX512VL iterator, masking, no g modifiers and "vm" input constraint,
another one with VI48_AVX iterator, !TARGET_AVX512VL in condition,
no masking, g modifiers and "v" input constraint, one with VI12_AVX512VL
iterator, no masking, no g modifiers and "vm" input constraint and last one with
VI12_AVX2 iterator, !TARGET_AVX512VL in condition, no masking, g modifiers
and "v" input constraint, but I think having one pattern is shorter than
that.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR target/94343
	* config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
	!TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
	operand is a register.  Don't enable masked variants for V*[QH]Imode.

	* gcc.target/i386/avx512f-pr94343.c: New test.
	* gcc.target/i386/avx512vl-pr94343.c: New test.

	PR rtl-optimization/87716
	* gcc.target/i386/pr57193.c: XFAIL a test-case.

	PR testsuite/94402
	* gfortran.dg/vect/vect-8.f90: Allow 22 or 23 loops
	to be vectorized (based on libmvec presence).

The AVX512F documentation clearly states that in instructions where the
destination is a memory only merging-masking is possible, not zero-masking,
and the assembler enforces that.

The testcase in this patch fails to assemble because of
Error: unsupported masking for `vextracti32x8'
on
        vextracti32x8   $0x0, %zmm1, -64(%rsp){%k1}{z}
For the vector extraction patterns, we apparently have 7 *_maskm patterns
that only accept memory destinations and rtx_equal_p merge-masking source
for it, 7 *<mask_name> corresponding patterns that allow memory destination
only for the non-masked cases (through <store_mask_constraint>), then 2
*<mask_name> patterns (lo ssehalf V16FI and lo ssehalf VI8F_256 ones) which
do allow memory destination even for masked cases and are the cause of the
testsuite failure, because we must not allow C constraint if the destination
is m, and finally one pair of patterns (separate * and *_mask, hi ssehalf
VI4F_256), which has another issue (for which I don't have a testcase
though), where if it would match zero-masking with register destination,
it wouldn't emit the needed {z} into assembly.
The attached patch fixes those 3 issues only, perhaps more suitable for
backporting.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR target/93069
	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
	<store_mask_constraint> instead of m in output operand constraint.
	(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
	%{%3%}.

	* gcc.target/i386/avx512vl-pr93069.c: New test.
	* gcc.dg/vect/pr93069.c: New test.

-mlongcall -mno-pltseq is supposed to emit long calls by using
indirect calls.  It differs from -mlongcall -mpltseq in that the
function addresses are not placed in the PLT and thus lazy PLT
resolution is not available, affecting programs that dlopen shared
libraries.

In the case of -mcpu=future -mpcrel -mlongcall -mno-pltseq we see an
indirect call being generated, but combine merrily optimises the
sequence back to a direct call.  call_indirect_pcrel is enough like
call_nonlocal_aix that this can happen.

This patch puts the call cookie back in the call rtl, removed by git
commit f90f960c, in order to disable the optimisation for long
calls.  When that is done for call_local_aix the pattern becomes the
same as call_local32/64, so I merged them.  The only difference
besides mode between call_local32 and call_local64, dating back to
1998 commit a260abc9, is that call_local64 has TARGET_64BIT in the
predicate.  That alone doesn't seem reason enough to need separate
patterns; The P mode iterator selects DI on TARGET_64BIT anyway.

	* config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
	(rs6000_indirect_call_template_1): Adjust to suit.
	* config/rs6000/rs6000.md (call_local): Merge call_local32,
	call_local64, and call_local_aix.
	(call_value_local): Simlarly.
	(call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
	and disable pattern when CALL_LONG.
	(call_indirect_aix, call_value_indirect_aix): Adjust rtl.
	(call_indirect_elfv2, call_indirect_pcrel): Likewise.
	(call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.

Change -falign-functions=N to

    Align the start of functions to the next power-of-two greater than
    or equal to N.

Add

    If '-falign-labels' is greater than this value, then its value is
    used instead.

to -falign-loops=N and -falign-jumps=N.

	PR driver/94381
	* doc/invoke.texi: Update -falign-functions, -falign-loops and
	-falign-jumps documentation.

This patch adds cases for JSON and D header file generation flags in the
testsuite, and sets up the test accordingly to only compile, then check
that the expected output file exists.

Support has also been added for the DFLAGS test directive, which
disables testing with all default flag permutations.

gcc/testsuite/ChangeLog:

	* lib/gdc-utils.exp: (gdc-convert-args): Handle compilation test
	arguments -D, -H, -X, and set compilable_output_file_ext.
	(gdc-convert-test): Document and add cases DFLAGS and
	EXTRA_CPP_SOURCES.  Add dg-final entry for output generation tests,
	and set compilable_do_what to compile.
	(gdc-do-test): Define compilable_do_what, default to assemble.

Tests have been moved into runnable_cxx as part of upstream dmd 3e10e2dd2.

The extra flags required for tests that mix C++ and D are now limited to
only a small subset of tests, rather than applied to all tests across
gdc.dg and gdc.test.

Reviewed-on: https://github.com/dlang/dmd/pull/10980

gcc/testsuite/ChangeLog:

	* gdc.test/runnable_cxx/runnable_cxx.exp: New file.
	* lib/gdc-utils.exp (gdc-do-test): Add case for runnable_cxx.
	* lib/gdc.exp (gdc_include_flags): Only add flags for libstdc++-v3 if
	GDC_INCLUDE_CXX_FLAGS is true.
	(gdc_link_flags): Likewise.
	(gdc_init): Move setting of default gdc test flags to...
	(gdc_target_compile): ...here.

	PR ipa/94363
	* cgraphunit.c (process_function_and_variable_attributes): Remove
	double 'attribute' words.

	2020-03-29  John David Anglin  <dave.anglin@bell.net>

	* gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
	.align output.

Use multiple test scripts, one for each subdirectory containing test
files, instead of having one test script to manage them all.

This allows removing some workarounds, such as the need to create
symlinks in the test run directory.

gcc/testsuite/ChangeLog:

	* gdc.test/compilable/compilable.exp: New file.
	* gdc.test/fail_compilation/fail_compilation.exp: New file.
	* gdc.test/gdc-test.exp: Remove.
	* gdc.test/runnable/runnable.exp: New file.
	* lib/gdc-utils.exp: ...this.  Remove load_lib gdc-dg.exp.
	(dmd2dg): Rename to...
	(gdc-convert-test): ...this.
	(gdc-do-test): Add testcases parameter and remove subdir handling.

	* testsuite/20_util/is_constructible/value-2.cc: Fix test to account
	for changes due to parenthesized aggregate-initialization in C++20.
	* testsuite/20_util/time_point/cons/81468.cc: Fix test to not clash
	with std::chrono::sys_time in C++20.

My recent changes to reverse_iterator's comparisons was not the version
of the code (or tests) that I meant to commit, and broke the relational
operators. This fixes them to reverse the order of the comparisons on
the base() iterators.

This also replaces the SFINAE constraints in the return type of the
reverse_iterator and move_iterator comparisons with a requires-clause.
This ensures the constrained overloads are preferred to unconstrained
ones. This means the non-standard same-type overloads can be omitted for
C++20 because they're not needed to solve the problem with std::rel_ops
or the testsuite's greedy_ops::X type.

	* include/bits/stl_iterator.h (reverse_iterator): Use requires-clause
	to constrain C++20 versions of comparison operators. Fix backwards
	logic of relational operators.
	(move_iterator): Use requires-clause to constrain comparison operators
	in C++20. Do not declare non-standard same-type overloads for C++20.
	* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: Check result
	of comparisons and check using greedy_ops type.
	* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc: Likewise.
	* testsuite/24_iterators/move_iterator/greedy_ops.cc: Remove redundant
	main function from compile-only test.
	* testsuite/24_iterators/reverse_iterator/greedy_ops.cc: Likewise.

Without this patch tortured tests eventually fail because of another
known issue which I plan to fix later in stage1.

	* gcc.dg/torture/pr87197-debug-sms.c: Move to ...
	* gcc.dg/sms-compare-debug-1.c: ... this.  Add -O2.
	* gcc.c-torture/execute/pr70127-debug-sms.c: Move to ...
	* gcc.dg/sms-compare-debug-2.c: ... this.  Add -O2.

	PR fortran/94348
	* decl.c (gfc_match_submod_proc): Add result var to the
	proc's namespace.

	PR fortran/94348
	* gfortran.dg/module_procedure_3.f90: New.

This adds support to detect and recover from the case where an opening brace
immediately follows the start of a requires-clause.  So rather than emitting the
error

  error: expected primary-expression before '{' token

followed by a slew of irrevelant errors, we now assume the user had intended to
write "requires requires {" and diagnose and recover accordingly.

gcc/cp/ChangeLog:

	PR c++/94306
	* parser.c (cp_parser_requires_clause_opt): Diagnose and recover from
	"requires {" when "requires requires {" was probably intended.

gcc/testsuite/ChangeLog:

	PR c++/94306
	* g++.dg/concepts/diagnostic8.C: New test.

This PR shows that a REQUIRES_EXPR outside of a template can sometimes be
misevaluated.  This happens because the evaluation routine tsubst_requires_expr
(and diagnose_requires_expr) assumes the REQUIRES_EXPR's subtrees are templated
trees and that therefore it's safe to call tsubst_expr on them.  But this
assumption isn't valid when we've parsed a REQUIRES_EXPR outside of a template
context.  In order to make this assumption valid here, this patch sets
processing_template_decl to non-zero before parsing the body of a REQUIRES_EXPR
so that its subtrees are indeed always templated trees.

gcc/cp/ChangeLog:

	PR c++/94252
	* constraint.cc (tsubst_compound_requirement): Always suppress errors
	from type_deducible_p and expression_convertible_p, as they're not
	substitution errors.
	(diagnose_atomic_constraint) <case INTEGER_CST>: Remove this case so
	that we diagnose INTEGER_CST expressions of non-bool type via the
	default case.
	* cp-gimplify.c (cp_genericize_r) <case REQUIRES_EXPR>: New case.
	* parser.c (cp_parser_requires_expression): Always parse the requirement
	body as if we're processing a template, by temporarily incrementing
	processing_template_decl.  Afterwards, if we're not actually in a
	template context, perform semantic processing to diagnose any invalid
	types and expressions.
	* pt.c (tsubst_copy_and_build) <case REQUIRES_EXPR>: Remove dead code.
	* semantics.c (finish_static_assert): Explain an assertion failure
	when the condition is a REQUIRES_EXPR like we do when it is a concept
	check.

gcc/testsuite/ChangeLog:

	PR c++/94252
	* g++.dg/concepts/diagnostic7.C: New test.
	* g++.dg/concepts/pr94252.C: New test.
	* g++.dg/cpp2a/concepts-requires18.C: Adjust to expect an additional
	diagnostic.

The previous patch tries to avoid changing our current default diagnostics.  But
for the sake of consistency we arguably should also respect
current_constraint_diagnosis_depth in diagnose_compound_requirement() like we do
in the other error-replaying diagnostic routines.  But doing so would be a
change to our default diagnostics behavior, so the change has been split out
into this separate patch for separate consideration.

gcc/cp/ChangeLog:

	* constraint.cc (diagnose_compound_requirement): When diagnosing a
	compound requirement, maybe replay the satisfaction failure, subject to
	the current diagnosis depth.

gcc/testsuite/ChangeLog:

	* g++.dg/concepts/diagnostic1.C: Pass -fconcepts-diagnostics-depth=2.
	* g++.dg/concepts/diagnostic5.C: Adjust expected diagnostics.
	* g++.dg/cpp2a/concepts-iconv1.C: Pass -fconcepts-diagnostics-depth=2.
	* g++.dg/cpp2a/concepts-requires5.C: Likewise.