[ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic variant support.

For the following MVE ACLE intrinsics, polymorphic variant support is missing on the trunk.

vbicq_n_s16, vbicq_n_s32, vbicq_n_u16 and vbicq_n_u32.

This patch add the polymorphic variant support for above intrinsics.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
	variant.
	(__arm_vbicq): Likewise.

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.

gcc/ChangeLog

+2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+	* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
+	variant.
+	(__arm_vbicq): Likewise.
+
 2020-0-31  Vineet Gupta <vgupta@synopsys.com>
 
 	* config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.

gcc/config/arm/arm_mve.h

@@ -20704,6 +20704,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -24073,6 +24077,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \

gcc/testsuite/ChangeLog

 2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
+	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
+
+2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
 	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Modify.
 	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
 	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.

gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c

@@ -10,4 +10,10 @@ foo (int16x8_t a)
   return vbicq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vbic.i16"  }  } */
+int16x8_t
+foo1 (int16x8_t a)
+{
+  return vbicq (a, 1);
+}
+
+/* { dg-final { scan-assembler-times "vbic.i16" 2 }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c

@@ -10,4 +10,10 @@ foo (int32x4_t a)
   return vbicq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vbic.i32"  }  } */
+int32x4_t
+foo1 (int32x4_t a)
+{
+  return vbicq (a, 1);
+}
+
+/* { dg-final { scan-assembler-times "vbic.i32" 2 }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c

@@ -10,4 +10,10 @@ foo (uint16x8_t a)
   return vbicq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vbic.i16"  }  } */
+uint16x8_t
+foo1 (uint16x8_t a)
+{
+  return vbicq (a, 1);
+}
+
+/* { dg-final { scan-assembler-times "vbic.i16" 2 }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c

@@ -10,4 +10,10 @@ foo (uint32x4_t a)
   return vbicq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vbic.i32"  }  } */
+uint32x4_t
+foo1 (uint32x4_t a)
+{
+  return vbicq (a, 1);
+}
+
+/* { dg-final { scan-assembler-times "vbic.i32" 2 }  } */