* ira.c (add_store_equivs, combine_and_move_insns): New functions,
	split out from..
	(update_reg_equivs): ..here.  Move allocation and freeing of
	reg_equiv, and calls to grow_reg_equivs, init_alias_analysis,
	end_alias_analysis to..
	(ira): ..here.

From-SVN: r235657

Where pdx_subregs[regno] is used, reg_equiv[regno] is also used.

	* ira.c (pdx_subregs): Delete.
	(struct equivalence): Add pdx_subregs field.
	(set_paradoxical_subreg): Remove pdx_subregs param.  Update
	pdx_subregs access.
	(update_equiv_regs): Don't create or free pdx_subregs.  Update
	pdx_subregs access.

From-SVN: r235656

[gcc]

2016-04-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.h: Change definitions of vec_xl and
	vec_xst.
	* config/rs6000/rs6000-builtin.def (LD_ELEMREV_V2DF): New.
	(LD_ELEMREV_V2DI): New.
	(LD_ELEMREV_V4SF): New.
	(LD_ELEMREV_V4SI): New.
	(LD_ELEMREV_V8HI): New.
	(LD_ELEMREV_V16QI): New.
	(ST_ELEMREV_V2DF): New.
	(ST_ELEMREV_V2DI): New.
	(ST_ELEMREV_V4SF): New.
	(ST_ELEMREV_V4SI): New.
	(ST_ELEMREV_V8HI): New.
	(ST_ELEMREV_V16QI): New.
	(XL): New.
	(XST): New.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	descriptions for VSX_BUILTIN_VEC_XL and VSX_BUILTIN_VEC_XST.
	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Map from
	TARGET_P9_VECTOR to RS6000_BTM_P9_VECTOR.
	(altivec_expand_builtin): Add handling for
	VSX_BUILTIN_ST_ELEMREV_<MODE> and VSX_BUILTIN_LD_ELEMREV_<MODE>.
	(rs6000_invalid_builtin): Add error-checking for
	RS6000_BTM_P9_VECTOR.
	(altivec_init_builtins): Define builtins used to implement vec_xl
	and vec_xst.
	(rs6000_builtin_mask_names): Define power9-vector.
	* config/rs6000/rs6000.h (MASK_P9_VECTOR): Define.
	(RS6000_BTM_P9_VECTOR): Define.
	(RS6000_BTM_COMMON): Include RS6000_BTM_P9_VECTOR.
	* config/rs6000/vsx.md (vsx_ld_elemrev_v2di): New define_insn.
	(vsx_ld_elemrev_v2df): Likewise.
	(vsx_ld_elemrev_v4sf): Likewise.
	(vsx_ld_elemrev_v4si): Likewise.
	(vsx_ld_elemrev_v8hi): Likewise.
	(vsx_ld_elemrev_v16qi): Likewise.
	(vsx_st_elemrev_v2df): Likewise.
	(vsx_st_elemrev_v2di): Likewise.
	(vsx_st_elemrev_v4sf): Likewise.
	(vsx_st_elemrev_v4si): Likewise.
	(vsx_st_elemrev_v8hi): Likewise.
	(vsx_st_elemrev_v16qi): Likewise.
	* doc/extend.texi: Add prototypes for vec_xl and vec_xst.  Correct
	grammar.

[gcc/testsuite]

2016-04-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/vsx-elemrev-1.c: New.
	* gcc.target/powerpc/vsx-elemrev-2.c: New.
	* gcc.target/powerpc/vsx-elemrev-3.c: New.
	* gcc.target/powerpc/vsx-elemrev-4.c: New.

From-SVN: r235654

2016-04-29  Patrick Palka  <ppalka@gcc.gnu.org>

	* tree-ssa-threadedge.c (simplify_control_stmt_condition): Split
	out into ...
	(simplify_control_stmt_condition_1): ... here.  Recurse into
	BIT_AND_EXPRs and BIT_IOR_EXPRs.

	* gcc.dg/tree-ssa/ssa-thread-14.c: New test.
	* gcc.dg/tree-ssa/ssa-thread-11.c: Update expected output.

From-SVN: r235653

	gcc/c-family/
	PR middle-end/70626
	* c-common.h (c_oacc_split_loop_clauses): Add boolean argument.
	* c-omp.c (c_oacc_split_loop_clauses): Use it to duplicate
	reduction clauses in acc parallel loops.

	gcc/c/
	PR middle-end/70626
	* c-parser.c (c_parser_oacc_loop): Don't augment mask with
	OACC_LOOP_CLAUSE_MASK.
	(c_parser_oacc_kernels_parallel): Update call to
	c_oacc_split_loop_clauses.

	gcc/cp/
	PR middle-end/70626
	* parser.c (cp_parser_oacc_loop): Don't augment mask with
	OACC_LOOP_CLAUSE_MASK.
	(cp_parser_oacc_kernels_parallel): Update call to
	c_oacc_split_loop_clauses.

	gcc/fortran/
	PR middle-end/70626
	* trans-openmp.c (gfc_trans_oacc_combined_directive): Duplicate
	the reduction clause in both parallel and loop directives.

	gcc/testsuite/
	PR middle-end/70626
	* c-c++-common/goacc/combined-reduction.c: New test.
	* gfortran.dg/goacc/reduction-2.f95: Add check for kernels reductions.

	libgomp/
	PR middle-end/70626
	* testsuite/libgomp.oacc-c++/template-reduction.C: Adjust test.
	* testsuite/libgomp.oacc-c-c++-common/combined-reduction.c: New test.
	* testsuite/libgomp.oacc-fortran/combined-reduction.f90: New test.

From-SVN: r235651

    
	* Make-lang.in (GO_OBJS): Remove go/dataflow.o, go/escape.o.

    Reviewed-on: https://go-review.googlesource.com/18261

From-SVN: r235649

Since PIC leads to the *movdi_internal pattern, check for nonexistence
of the *movdi_internal pattern in PR target/70155 tests only if PIC is
off.

	* gcc.target/i386/pr70155-1.c: Check for nonexistence of the
	*movdi_internal pattern only if PIC off.
	* gcc.target/i386/pr70155-2.c: Likewise.
	* gcc.target/i386/pr70155-3.c: Likewise.
	* gcc.target/i386/pr70155-4.c: Likewise.
	* gcc.target/i386/pr70155-5.c: Likewise.
	* gcc.target/i386/pr70155-6.c: Likewise.
	* gcc.target/i386/pr70155-7.c: Likewise.
	* gcc.target/i386/pr70155-8.c: Likewise.
	* gcc.target/i386/pr70155-15.c: Likewise.
	* gcc.target/i386/pr70155-17.c: Likewise.
	* gcc.target/i386/pr70155-22.c: Likewise.

From-SVN: r235647

        PR target/69810
        * config/rs6000/rs6000.md (EXTQI): Don't allow extension to HImode.
        (zero_extendqi<mode>2_dot): Revert earlier conversion from
        define_insn_and_split to define_insn.
        (zero_extendqi<mode>2_dot2): Same.
        (extendqi<mode>2_dot): Same.
        (extendqi<mode>2_dot2): Same.

From-SVN: r235646

2016-04-29  Chris Gregory  <czipperz@gmail.com>

	* config/*: Remove trailing whitespace.
	* src/*: Likewise.
	* testsuite/tr1/*: Likewise.
	* testsuite/util/*: Likewise.

From-SVN: r235645

	gcc/testsuite/ChangeLog
	PR tree-optimization/70803
	* gcc.dg/vect/pr56625.c: Require vect_int_mult.

From-SVN: r235644

include/
	* dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
	DW_LANG_Rust_old>: New constants.

From-SVN: r235643

	* config/i386/i386.md (unspec): Add UNSPEC_PROBE_STACK.
	(probe_stack): New expander.
	(probe_stack_<mode>): New insn pattern.

From-SVN: r235642

	* config/i386/i386.md
	(operations with memory inputs setting flags peephole2):
	Remove uneeded REG_P checks.  Cleanup pattern generation.

From-SVN: r235641

libgcc/
	* config/sh/crt1.S: Remove SH5 support.
	* config/sh/crti.S: Likewise.
	* config/sh/crtn.S: Likewise.
	* config/sh/lib1funcs-4-300.S: Likewise.
	* config/sh/lib1funcs-Os-4-200.S: Likewise.
	* config/sh/lib1funcs.S: Likewise.
	* config/sh/linux-unwind.h: Likewise.
	* config/sh/t-sh64: Delete.

From-SVN: r235640

tree-vect-loop.c (vect_transform_loop): Fix nb_iterations_upper_bound computation for vectorized loop.

gcc/

	* tree-vect-loop.c (vect_transform_loop): Fix
	nb_iterations_upper_bound computation for vectorized loop.

gcc/testsuite/

	* gcc.target/i386/vect-unpack-2.c (avx512bw_test): Avoid
	optimization of vector loop.
	* gcc.target/i386/vect-unpack-3.c: New test.
	* gcc.dg/vect/vect-nb-iter-ub-1.c: New test.
	* gcc.dg/vect/vect-nb-iter-ub-2.c: New test.
	* gcc.dg/vect/vect-nb-iter-ub-3.c: New test.

From-SVN: r235639

	PR c/70852
	* c-common.c (warn_for_memset): Check domain before accessing it.

	* gcc.dg/pr70852.c: New test.

From-SVN: r235638

re PR sanitizer/70342 (g++ -fsanitize=undefined never finishes compiling (>24h) in qtxmlpatterns test suite)

	PR sanitizer/70342
	* fold-const.c (tree_single_nonzero_warnv_p): For TARGET_EXPR, use
	TARGET_EXPR_SLOT as a base.

	* g++.dg/ubsan/null-7.C: New test.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>

From-SVN: r235637

arc.md (*loadqi_update): Replace use of 'rI' constraint with 'rCm2' constraints to limit possible...

2016-04-29  Andrew Burgess  <andrew.burgess@embecosm.com>

        * config/arc/arc.md (*loadqi_update): Replace use of 'rI'
        constraint with 'rCm2' constraints to limit possible immediate
        size.
        (*load_zeroextendqisi_update): Likewise.
        (*load_signextendqisi_update): Likewise.
        (*loadhi_update): Likewise.
        (*load_zeroextendhisi_update): Likewise.
        (*load_signextendhisi_update): Likewise.
        (*loadsi_update): Likewise.
        (*loadsf_update): Likewise.

From-SVN: r235636

	* config/i386/predicates.md (constm1_operand): Fix comparison.

From-SVN: r235635

gcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gcc.target/arc/ieee_eq.c: New test.

libgcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/ieee-754/eqdf2.S: Handle FPX NaN.

From-SVN: r235633

include/
	* longlong.h (umul_ppmm): Remove SHMEDIA checks.
	(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.

gcc/
	* common/config/sh/sh-common.c (sh_option_optimization_table): Remove
	remaining SH5 related settings.
	* config/sh/sh-protos.h (shmedia_cleanup_truncate,
	shmedia_prepare_call_address): Delete.
	* config/sh/sh.c (sh_print_operand, output_stack_adjust,
	DWARF_CIE_DATA_ALIGNMENT, LOCAL_ALIGNMENT): Update comments.
	* config/sh/sh.h (SUBTARGET_ASM_RELAX_SPEC,
	UNSUPPORTED_SH2A): Remove m5 checks.
	(sh_divide_strategy_e): Remove SH5 division strategies.
	(TARGET_PTRMEMFUNC_VBIT_LOCATION): Remove and use default.
	* config/sh/sh.md (divsf3): Reinstate define_expand pattern.

From-SVN: r235632

include/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* longlong.h (add_ssaaaa): Replace obsolete 'J' constraint with
	'Cal' constraint.
	(sub_ddmmss): Likewise.

From-SVN: r235631

gcc/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/s390/s390.c (s390_rtx_costs): Update documentation.

From-SVN: r235630

gcc/c-family/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	PR/69089
	* c-common.c (handle_aligned_attribute): Allow 0 as an argument to the
	"aligned" attribute.

gcc/testsuite/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	PR/69089
	* g++.dg/cpp0x/alignas6.C: New test.

From-SVN: r235629

The attached patch cleans up some (mostly unnecessary) dg-do
directives in the gcc.dg and gcc.target test cases.

gcc/testsuite/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* gcc/testsuite/gcc.dg/cpp/mac-dir-2.c: Remove pointless duplicate
	dg-do.
	* gcc/testsuite/gcc.dg/pr27003.c: Likewise.
	* gcc/testsuite/gcc.dg/tree-ssa/cswtch.c: Likewise.
	* gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c: Likewise.
	* gcc/testsuite/gcc.dg/tree-ssa/predcom-4.c: Likewise.
	* gcc/testsuite/gcc.dg/tree-ssa/predcom-5.c: Likewise.
	* gcc.target/arc/mxy.c: Likewise.
	* gcc.target/arc/mswape.c: Likewise.
	* gcc.target/arc/mrtsc.c: Likewise.
	* gcc.target/arc/mcrc.c: Likewise.
	* gcc.target/arc/mdsp-packa.c: Likewise.
	* gcc.target/arc/mdvbf.c: Likewise.
	* gcc.target/arc/mlock.c: Likewise.
	* gcc.target/arc/mmac-24.c: Likewise.
	* gcc.dg/spec-options.c: Switch order of the two "dg-do run".

From-SVN: r235628

For performance reasons it is important to write the full 64 bits of
an FPR target reg even when dealing with 32 bit values.  So we chose
lder over ler for 32 bit float register moves.  lder zero-extends the
32 bit value from the source reg to 64 bit in the target.  However,
since it actually doesn't matter whether we write the upper 32 bits
with zeros or with any other garbage we can also use ldr instead.  It
is bit shorter and therefore will do good for I-Cache usage.

gcc/ChangeLog:

2016-04-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/2964.md ("z13_unit_fxu", "z13_0"): Remove lder.
	* config/s390/s390.md ("movsi_larl", "*movsi_esa", "mov<mode>"):
	Change lder to ldr.
	* config/s390/vector.md ("mov<mode>"): Likewise.

From-SVN: r235627

This fixes an issue with the long displacement memory address
constraints S and T.  These were defined to only accept long
displacement addresses.  This is wrong since a memory constraint must
not reject an address with a 0 displacement.  Reload relies on being
able to turn an invalid memory address into a valid one by reloading
the address into a base register.  The S and T constraints would
reject such an address.

This isn't really a problem for the backend since we used the
constraints with that knowledge there but it is a problem for people
writing inline assemblies.

gcc/ChangeLog:

2016-04-29  Ulrich Weigand  <uweigand@de.ibm.com>

	* config/s390/constraints.md ("U", "W"): Invoke
	s390_mem_constraint with "ZR" and "ZT".
	* config/s390/s390.c (s390_check_qrst_address): Reject invalid
	addresses when using LRA.  Accept also short displacements for S
	and T constraints.  Do not check for long displacement target for
	S and T constraints.
	(s390_mem_constraint): Remove handling of U and W constraints.
	* config/s390/s390.md (various patterns): Remove the short
	displacement constraints (Q and R) if a long displacement
	constraint is present.  Add longdisp as required CPU capability.
	* config/s390/vector.md: Likewise.
	* config/s390/vx-builtins.md: Likewise.

From-SVN: r235626

	PR target/60040
	* reload1.c (reload): Call finish_spills before
	restarting reload loop. Skip select_reload_regs
	if update_eliminables_and_spill returns true.

testsuite/
	PR target/60040
	* gcc.target/avr/pr60040-1.c: New.
	* gcc.target/avr/pr60040-2.c: New.

From-SVN: r235625

2016-04-29  Richard Biener  <rguenther@suse.de>

	* gcc.dg/tree-ssa/pr18589-10.c: Adjust.

From-SVN: r235624

The combine pass may conclude umulhisi3_imm pattern can accept also sign
extended 16-bit constants. This patch prohibits the combine in considering
this pattern as suitable.

gcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define.
	* config/arc/arc.md (umulhisi3): Use arc_short_operand predicate.
	(umulhisi3_imm): Update predicates and constraint letters.
	(umulhisi3_reg): Declare instruction as commutative.
	* config/arc/constraints.md (J12, J16): New constraints.
	* config/arc/predicates.md (short_unsigned_const_operand): New
	predicate.
	(arc_short_operand): Likewise.
	* testsuite/gcc.target/arc/umulsihi3_z.c: New file.

From-SVN: r235623

re PR tree-optimization/13962 ([tree-ssa] make "fold" use alias information to optimize pointer comparisons)

2016-04-29  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/13962
	PR tree-optimization/65686
	* tree-ssa-alias.h (ptrs_compare_unequal): Declare.
	* tree-ssa-alias.c (ptrs_compare_unequal): New function
	using PTA to compare pointers.
	* match.pd: Add pattern for pointer equality compare simplification
	using ptrs_compare_unequal.

	* gcc.dg/uninit-pr65686.c: New testcase.

From-SVN: r235622

2016-04-29  Richard Biener  <rguenther@suse.de>

	* stor-layout.c (layout_type): Do not build a pointer-to-element
	type for arrays.

From-SVN: r235621

	* config/i386/i386.md (Load+RegOp to Mov+MemOp peephole2):
	Use SWI mode iterator.  Use general_reg_operand predicate.
	(Load+RegOp to Mov+MemOp peephole2 with vector regs): Split
	peephole to MMX and SSE part.  Use mmx_reg_operand and sse_reg_operand
	predicates.

From-SVN: r235620

From-SVN: r235619

	PR middle-end/70843
	* fold-const.c (operand_equal_p): Don't verify hash value equality
	if arg0 == arg1.
	* tree.c (inchash::add_expr): Handle STATEMENT_LIST.  Ignore BLOCK
	and OMP_CLAUSE.

	* gcc.dg/pr70843.c: New test.

From-SVN: r235615

c-array-notation.c (fix_builtin_array_notation_fn): Fix final argument to build_modify_expr in two cases.

2016-04-28  Andrew MacLeod  <amacleod@redhat.com>

	* c-array-notation.c (fix_builtin_array_notation_fn): Fix final
	argument to build_modify_expr in two cases.

From-SVN: r235614

    
    If a call expression is executed in an independent goroutine via
    use of a Go statement, mark it as concurrent.
    
    Reviewed-on: https://go-review.googlesource.com/18700

From-SVN: r235608

	PR target/70858
	* config/i386/i386.c (bdesc_special_args): Add | OPTION_MASK_ISA_64BIT
	to __builtin_ia32_lwpval64 and __builtin_ia32_lwpins64.
	(bdesc_args): Add | OPTION_MASK_ISA_64BIT to __builtin_ia32_bextr_u64,
	__builtin_ia32_bextri_u64, __builtin_ia32_bzhi_di,
	__builtin_ia32_pdep_di and __builtin_ia32_pext_di.

	* gcc.target/i386/pr70858.c: New test.

From-SVN: r235607

- Rename "info_ptr" to "info", as in all other routines;
- Don't set fields to 0, the whole struct already is set to 0;
- Fix formatting a bit.


	* config/rs6000/rs6000.c (compute_save_world_info): Rename info_ptr
	to info.  Don't initialize separate fields to 0.  Clean up
	formatting a bit.

From-SVN: r235606

2016-04-28  Andrew Burgess  <andrew.burgess@embecosm.com>

        * gcc.target/arc/nps400-1.c: New file.

From-SVN: r235603