From-SVN: r254516

From-SVN: r254513

https://gcc.gnu.org/ml/gcc-patches/2017-11/msg00498.html
2017-11-07 Boris Kolpackov  <boris@codesynthesis.com>
	* Make-lang.in (CP_PLUGIN_HEADERS): Add operators.def since included
	in cp-tree.h.

From-SVN: r254512

	PR c++/82835
	* cp-gimplify.c (cxx_omp_clause_apply_fn): For methods pass i - 1 to
	convert_default_arg instead of i.

	* testsuite/libgomp.c++/pr82835.C: New test.

From-SVN: r254511

	PR target/82855
	* config/i386/i386.md (SWI1248_AVX512BWDQ2_64): New mode iterator.
	(*cmp<mode>_ccz_1): New insn with $k alternative.

	* gcc.target/i386/avx512dq-pr82855.c: New test.

From-SVN: r254510

	PR target/82855
	* config/i386/i386.c (ix86_swap_binary_operands_p): Treat
	RTX_COMM_COMPARE as commutative as well.
	(ix86_binary_operator_ok): Formatting fix.
	* config/i386/sse.md (*mul<mode>3<mask_name><round_name>,
	*<code><mode>3<mask_name><round_saeonly_name>,
	*<code><mode>3<mask_name>, *<code>tf3, *mul<mode>3<mask_name>,
	*<s>mul<mode>3_highpart<mask_name>,
	*vec_widen_umult_even_v16si<mask_name>,
	*vec_widen_umult_even_v8si<mask_name>,
	*vec_widen_umult_even_v4si<mask_name>,
	*vec_widen_smult_even_v16si<mask_name>,
	*vec_widen_smult_even_v8si<mask_name>, *sse4_1_mulv2siv2di3<mask_name>,
	*avx2_pmaddwd, *sse2_pmaddwd, *<sse4_1_avx2>_mul<mode>3<mask_name>,
	*avx2_<code><mode>3, *avx512f_<code><mode>3<mask_name>,
	*sse4_1_<code><mode>3<mask_name>, *<code>v8hi3,
	*sse4_1_<code><mode>3<mask_name>, *<code>v16qi3, *avx2_eq<mode>3,
	<avx512>_eq<mode>3<mask_scalar_merge_name>_1, *sse4_1_eqv2di3,
	*sse2_eq<mode>3, <mask_codefor><code><mode>3<mask_name>,
	*<code><mode>3, *<sse2_avx2>_uavg<mode>3<mask_name>,
	*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, *ssse3_pmulhrswv4hi3): Use
	!(MEM_P (operands[1]) && MEM_P (operands[2])) condition instead of
	ix86_binary_operator_ok.  Formatting fixes.
	(*<plusminus_insn><mode>3<mask_name><round_name>,
	*<plusminus_insn><mode>3, *<plusminus_insn><mode>3_m): Formatting
	fixes.

From-SVN: r254509

We currently generate (sometimes pretty long) sequences of integer
insns to implement the various cstore patterns.  If the CPU has a fast
isel, we can use that at the same latency as of just two integer insns
(you also get a load immediate of 1, and sometimes one of 0 as well,
but those are not in the critical path: they don't depend on any other
instruction).

There are a few patterns that already are implemented with just two
instructions; so don't use isel in that case (I still need to check
all lt/gt/ltu/gtu/le/leu/ge/geu patterns with all SI/DI combinations,
one or two might be better without isel).

This introduces a new GPR2 mode iterator, for those patterns that use
two independent integer modes.


	* config/rs6000/rs6000.md (GPR2): New mode_iterator.
	("cstore<mode>4"): Don't always expand with rs6000_emit_int_cmove for
	eq and ne if TARGET_ISEL.
	(cmp): New code_iterator.
	(UNS, UNSU_, UNSIK): New code_attrs.
	(<code><GPR:mode><GPR2:mode>2_isel): New define_insn_and_split.
	("eq<mode>3"): New define_expand, rename the define_insn_and_split
	to...
	("eq<mode>3"): ... this.
	("ne<mode>3"): New define_expand, rename the define_insn_and_split
	to...
	("ne<mode>3"): ... this.

From-SVN: r254508

gcc/
	PR target/82812
	* common/config/i386/i386-common.c
	(OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag.
	(ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags.
	* config/i386/i386-c.c (ix86_target_macros_internal): Ditto.
	* config/i386/i386.opt: Ditto.
	* config/i386/i386.c (ix86_target_string): Ditto.
	(ix86_option_override_internal): Ditto.
	(ix86_init_mpx_builtins): Move MPX to args2.
	(ix86_expand_builtin): Special handling for OPTION_MASK_ISA_GFNI.
	* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi,
	__builtin_ia32_vgf2p8affineinvqb_v64qi_mask,
	__builtin_ia32_vgf2p8affineinvqb_v32qi,
	__builtin_ia32_vgf2p8affineinvqb_v32qi_mask,
	__builtin_ia32_vgf2p8affineinvqb_v16qi,
	__builtin_ia32_vgf2p8affineinvqb_v16qi_mask): Move to ARGS array.

From-SVN: r254507

	* src/filesystem/ops-common.h (make_file_type) [S_ISSOCK]: Only use
	S_ISSOCK when defined.

From-SVN: r254506

	PR target/80425
	* config/i386.i386.md (*zero_extendsidi2): Change (?r,*Yj), (?*Yi,r)
	and (*x,m) to ($r,Yj), ($Yi,r) and ($x,m).
	(zero-extendsidi peephole2): Remove peephole.

testsuite/ChangeLog:

	PR target/80425
	* gcc.target/i386/pr80425-3.c: New test.

From-SVN: r254505

    
    Nested functions are named "outerfunc.$nestedN", where N is a
    number. nested_function_num extracts that number. The name is
    first passed to unpack_hidden_name, which handles the "." and
    should result "$nestedN". Don't expect the "." again.
    
    This fixes assertion failure when escape analysis is enabled
    and -fgo-debug-escape is on. The failure looks
    
    go1: internal compiler error: in nested_function_num, at go/gofrontend/names.cc:241
    0x7bd7d3 Gogo::nested_function_num(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)
    
    Reviewed-on: https://go-review.googlesource.com/76213

From-SVN: r254504

	PR c/53037
	* stor-layout.c: Include attribs.h.
	(handle_warn_if_not_align): Replace test on TYPE_USER_ALIGN with
	explicit lookup of "aligned" attribute.

From-SVN: r254503

From-SVN: r254502

Without this we aren't getting proper memcpy inlining on RISC-V systems,
which is particularly disastrous for Dhrystone performance on RV32IM
systems.

gcc/ChangeLog

2017-11-07  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv-protos.h (riscv_hard_regno_nregs): New
        prototype.
        (riscv_expand_block_move): Likewise.
        gcc/config/riscv/riscv.h (MOVE_RATIO): Tune cost to movmemsi
        implementation.
        (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER): New define.
        (RISCV_MAX_MOVE_BYTES_STRAIGHT): New define.
        gcc/config/riscv/riscv.c (riscv_block_move_straight): New
        function.
        (riscv_adjust_block_mem): Likewise.
        (riscv_block_move_loop): Likewise.
        (riscv_expand_block_move): Likewise.
        gcc/config/riscv/riscv.md (movmemsi): New pattern.

From-SVN: r254501

Use no suffix at all in the musl dynamic linker name for hard
float ABI. Use -sf and -sp suffixes in musl dynamic linker name
for soft float and single precision ABIs. The following table
outlines the musl interpreter names for the RISC-V ABI names.

musl interpreter        | RISC-V ABI
----------------------- | -------------
ld-musl-riscv32.so.1    | riscv32-ilp32d
ld-musl-riscv64.so.1    | riscv64-lp64d
ld-musl-riscv32-sf.so.1 | riscv32-ilp32
ld-musl-riscv64-sf.so.1 | riscv64-lp64
ld-musl-riscv32-sp.so.1 | riscv32-ilp32f
ld-musl-riscv64-sp.so.1 | riscv64-lp64f

gcc/ChangeLog

2017-11-06  Michael Clark  <michaeljclark@mac.com>

        * config/riscv/linux.h (MUSL_ABI_SUFFIX): New define.
        (MUSL_DYNAMIC_LINKER): Likewise.

From-SVN: r254500

Some of the shift expanders accepted nonmemory_operands but were only
able to handle register_operands or CONST_INTs.  This is probably
academic without SVE, since we're not likely to see shifts by other
types of constant (const_wide_ints, consts, etc).  But for SVE,
it's possible for a vectorised shift induction to have a CONST_POLY_INT
shift amount.

This patch makes the expanders use aarch64_reg_or_imm instead.

2017-11-07  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
	(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
	nonmmory_operand.

From-SVN: r254499

2017-11-07  Richard Biener  <rguenther@suse.de>

	* match.pd: Fix build.

From-SVN: r254498

Canonicalize x / (- y) into (-x) / y.

This moves negates out of the RHS of a division in order to
allow further simplifications and potentially more reciprocal CSEs.

2017-11-07  Wilco Dijkstra  <wdijkstr@arm.com>
	    Jackson Woodruff  <jackson.woodruff@arm.com>

    gcc/
	PR tree-optimization/71026
	* match.pd: Canonicalize negate in division.

    testsuite/
	PR 71026/tree-optimization/71026
	* gcc.dg/div_neg: New test.

From-SVN: r254497

Currently the code A << (B - C) is not simplified.
However at least a more specific case of 1U << (C -x) where
C = precision(type) - 1 can be simplified to (1 << C) >> x.

This is done by adding a new simplification rule in match.pd.

2017-11-07  Sudakshina Das  <sudi.das@arm.com>

    gcc/
	PR middle-end/80131
	* match.pd: Simplify 1 << (C - x) where C = precision (x) - 1.

    testsuite/
	PR middle-end/80131
	* testsuite/gcc.dg/pr80131-1.c: New Test.

From-SVN: r254496

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

gcc/
	* match.pd ((a&~b)|(a^b),(a&~b)^~a,(a|b)&~(a^b),a|~(a^b),
	(a|b)|(a&^b),(a&b)|~(a^b),~(~a&b),~X^Y): New transformations.

gcc/testsuite/
	* gcc.dg/tree-ssa/bitops-1.c: New file.

From-SVN: r254495

gcc/ChangeLog:

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

	* fold-const.c (negate_expr_p) [PLUS_EXPR, MINUS_EXPR]: Handle
	non-scalar integral types.
	* match.pd (negate_expr_p): Handle MINUS_EXPR.
	(-(A-B), -(~A)): New transformations.

gcc/testsuite/ChangeLog:

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

	* gcc.dg/tree-ssa/negminus.c: New test.

From-SVN: r254494

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	* config/powerpcspe/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove
	semicolon after "do {} while (0)".
	* config/powerpcspe/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.

From-SVN: r254493

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	* config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove semicolon
	after "do {} while (0)".
	* config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.

From-SVN: r254492

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	* config/rs6000/aix-unwind.h (REGISTER_CFA_OFFSET_FOR): Remove semicolon
	after "do {} while (0)".

From-SVN: r254491

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	PR other/82784
	* config/arm/arm.c (HANDLE_NARROW_SHIFT_ARITH): Remove semicolon after
	"while {} do (0)".
	(arm_rtx_costs_internal): Add missing semicolon after
	HANDLE_NARROW_SHIFT_ARITH call.

From-SVN: r254490

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	PR other/82784
	* config/aarch64/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Remove
	semicolon after "do {} while (0)".
	* config/i386/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
	* config/ia64/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
	* config/mips/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
	* config/rs6000/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.

From-SVN: r254489

	* typeck2.c (build_m_component_ref): Also accept in lower stds with
	a pedwarn.

From-SVN: r254487

gcc currently uses ngettext in a number of places (gcc/cp/pt.c,
gcc/diagnostic.c, gcc/collect2.c).  Apparently there are (or used to
be) gettext implementations that lack ngettext.  See config/gettext.m4.

This patch arranges for intl/ to be compiled when the system gettext
lacks ngettext.

	* configure.ac: Invoke AM_GNU_GETTEXT with need_ngettext.
	* configure: Regenerate.

From-SVN: r254486

We want to actually use isel, so we shouldn't disable it.  It is
already not set by default on CPUs that don't have it, or where we
do not want to use it.


	* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
	disable isel if it was not set explicitly.

From-SVN: r254485

FT32 makes use of multiple address spaces. When trying to inspect
objects in GDB, GDB was treating them as a straight "const". The cause
seems to be in GCC DWARF2 output.

This output is handled in gcc/gcc/dwarf2out.c, where modified_type_die()
checks that TYPE has qualifiers CV_QUALS. However while TYPE has
ADDR_SPACE qualifiers, the modified_type_die() explicitly discards the
ADDR_SPACE qualifiers.

This patch retains the ADDR_SPACE qualifiers as modified_type_die()
outputs the DWARF type tree.  This allows the types to match, and correct
type information for the object is emitted.

[gcc]

2017-11-06  James Bowman  <james.bowman@ftdichip.com>

	* gcc/dwarf2out.c (modified_type_die): Retain ADDR_SPACE
	qualifiers.
        (add_type_attribute) likewise.

From-SVN: r254484

From-SVN: r254483

When there is no need to make a copy of ix86_frame, we can use reference
of struct ix86_frame to avoid copy.

Tested on x86-64.

	* config/i386/i386.c (ix86_can_use_return_insn_p): Use reference
	of struct ix86_frame.
	(ix86_initial_elimination_offset): Likewise.
	(ix86_expand_split_stack_prologue): Likewise.

From-SVN: r254480

	* gcc.target/i386/stack-check-12.c: Revert to initial version.  Then..
	Add -fomit-frame-pointer.

From-SVN: r254479

2017-11-06  Marc Glisse  <marc.glisse@inria.fr>

	* tree-vrp.h (enum value_range_type): Update stale comment.

From-SVN: r254478

2017-11-06  François Dumont  <fdumont@gcc.gnu.org>

	* testsuite/libstdc++-prettyprinters/tr1.cc:  Compile with -O0.

From-SVN: r254477

    
    Currently the runtime is hard-coded to non-escape in various places.
    Don't run escape analysis for runtime.
    
    Reviewed-on: https://go-review.googlesource.com/76210

From-SVN: r254476

    
    "make check" runs make recursively to check each package. Pass
    the flags through. So it is possible to run "make check" with
    different settings easily.
    
    Reviewed-on: https://go-review.googlesource.com/76029

From-SVN: r254475

This patch passes the number of units to aarch64_expand_vec_perm
and aarch64_expand_vec_perm_const, which avoids a to_constant ()
once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm)
	(aarch64_expand_vec_perm_const): Take the number of units too.
	* config/aarch64/aarch64.c (aarch64_expand_vec_perm)
	(aarch64_expand_vec_perm_const): Likewise.
	* config/aarch64/aarch64-simd.md (vec_perm_const<mode>)
	(vec_perm<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254469

This patch passes the number of units to aarch64_simd_vect_par_cnst_half,
which avoids a to_constant () once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half):
	Take the number of units too.
	* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise.
	(aarch64_simd_check_vect_par_cnst_half): Update call accordingly,
	but check for a vector mode before rather than after the call.
	* config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>)
	(move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>)
	(vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>)
	(vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>)
	(vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>)
	(aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3)
	(widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>)
	(aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>)
	(aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>)
	(aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>)
	(aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>)
	(aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>)
	(aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>)
	(aarch64_sqdmull2_n<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254468

This patch passes the number of units to aarch64_reverse_mask,
which avoids a to_constant () once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take
	the number of units too.
	* config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise.
	* config/aarch64/aarch64-simd.md (vec_load_lanesoi<mode>)
	(vec_store_lanesoi<mode>, vec_load_lanesci<mode>)
	(vec_store_lanesci<mode>, vec_load_lanesxi<mode>)
	(vec_store_lanesxi<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254467