We currently generate (sometimes pretty long) sequences of integer
insns to implement the various cstore patterns.  If the CPU has a fast
isel, we can use that at the same latency as of just two integer insns
(you also get a load immediate of 1, and sometimes one of 0 as well,
but those are not in the critical path: they don't depend on any other
instruction).

There are a few patterns that already are implemented with just two
instructions; so don't use isel in that case (I still need to check
all lt/gt/ltu/gtu/le/leu/ge/geu patterns with all SI/DI combinations,
one or two might be better without isel).

This introduces a new GPR2 mode iterator, for those patterns that use
two independent integer modes.


	* config/rs6000/rs6000.md (GPR2): New mode_iterator.
	("cstore<mode>4"): Don't always expand with rs6000_emit_int_cmove for
	eq and ne if TARGET_ISEL.
	(cmp): New code_iterator.
	(UNS, UNSU_, UNSIK): New code_attrs.
	(<code><GPR:mode><GPR2:mode>2_isel): New define_insn_and_split.
	("eq<mode>3"): New define_expand, rename the define_insn_and_split
	to...
	("eq<mode>3"): ... this.
	("ne<mode>3"): New define_expand, rename the define_insn_and_split
	to...
	("ne<mode>3"): ... this.

From-SVN: r254508