Sometimes the memory equivalent is not valid due to a large offset.
For example replacing the ap register with its fp/sp-equivalent during
LRA step. To solve this we introduced TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV.

gcc/
2017-08-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_cannot_substitute_mem_equiv_p): New function.
	(TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.

gcc/testsuite
2017-08-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/lra-1.c: New test.

From-SVN: r255273

[testsuite]

2017-11-29  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: Add xxspltib insn
	to expected output.
	* gcc.target/powerpc/fold-vec-abs-char.c: Add xxspltib insn
	to expected output.

From-SVN: r255272

	PR libstdc++/83226
	* include/bits/node_handle.h (_Node_handle::__pointer): Avoid forming
	pointer-to-reference types.
	* testsuite/23_containers/map/modifiers/insert/83226.cc: New test.

From-SVN: r255271

gcc/c-family/
	* c-common.h (inv_list): Remove.

From-SVN: r255270

re PR target/83210 (__builtin_mul_overflow() generates suboptimal code when exactly one argument is the constant 2)

	PR target/83210
	* internal-fn.c (expand_mul_overflow): Optimize unsigned
	multiplication by power of 2 constant into two shifts + comparison.

	* gcc.target/i386/pr83210.c: New test.

From-SVN: r255269

	PR target/81616
	* x86-tnue-costs.h (generic_cost): Revise for modern CPUs
	* gcc.target/i386/l_fma_double_1.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_2.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_3.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_4.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_5.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_6.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_1.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_2.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_3.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_4.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_5.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_6.c: Update count of fma instructions.

From-SVN: r255268

re PR tree-optimization/83202 (Try joining operations on consecutive array elements during tree vectorization)

2017-11-30  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/83202
	* tree-ssa-loop-ivcanon.c (try_unroll_loop_completely): Add
	allow_peel argument and guard peeling.
	(canonicalize_loop_induction_variables): Likewise.
	(canonicalize_induction_variables): Pass false.
	(tree_unroll_loops_completely_1): Pass unroll_outer to disallow
	peeling from cunrolli.

	* gcc.dg/vect/pr83202-1.c: New testcase.
	* gcc.dg/tree-ssa/pr61743-1.c: Adjust.

From-SVN: r255267

    
    The map zero value is a common symbol, and it doesn't really make
    sense to have a constant common symbol. Current GCC has started to
    reject this case, probably as part of the fix for PR 83100.
    
    Reviewed-on: https://go-review.googlesource.com/80877

From-SVN: r255266

	* config/abi/post/hppa-linux-gnu/baseline_symbols.txt: Update.

From-SVN: r255265

From-SVN: r255264

Eventually we should print the reason that any combination fails.
This is a good start (these happen often).


	* combine.c (try_combine): Print a message to dump file whenever
	I0, I1, or I2 cannot be combined into I3.

From-SVN: r255261

The fix for PR82621 makes us not split an I2 if one of the results of
those SETs is unused, since combine does not handle that properly.  But
this results in degradation for i386 (or more in general, for any
target that does not have patterns for parallels with an unused result
as a CLOBBER instead of a SET for that result).

This patch instead makes us not split only if one of the results is set
again before I3.  That fixes PR83156 and also fixes PR82621.

Unfortunately it undoes the nice optimisations that the previous patch
did on powerpc.


	PR rtl-optimization/83156
	PR rtl-optimization/82621
	* combine.c (try_combine): Don't split an I2 if one of the dests is
	set again before I3.  Allow unused dests.

From-SVN: r255260

This adds a second variant of the adde insn pattern, this one with the
CA register as the second operand.  The existing pattern has it as the
third operand.  It would be ideal if RTL was always canonicalised like
that, but it isn't (and that is not trivial), and this is a simple and
harmless patch.


	* config/rs6000/rs6000.md (*add<mode>3_carry_in_internal2): New.

From-SVN: r255259

2017-11-29  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/80818
	* lra.c (collect_non_operand_hard_regs): New arg insn.  Pass it
	recursively.  Use insn code for clobber.
	(lra_set_insn_recog_data): Pass the new arg to
	collect_non_operand_hard_regs.
	(add_regs_to_insn_regno_info): Pass insn instead of uid.  Use insn
	code for clobber.
	(lra_update_insn_regno_info): Pass insn to
	add_regs_to_insn_regno_info.

From-SVN: r255258

	gcc/
	* config/riscv/riscv.c (SINGLE_SHIFT_COST): New.
	(riscv_rtx_costs): Case ZERO_EXTRACT, match new pattern, and return
	SINGLE_SHIFT_COST.  Case LT and ZERO_EXTEND, likewise.  Case ASHIFT,
	use SINGLE_SHIFT_COST.
	* config/riscv/riscv.md (lshrsi3_zero_extend_1): New.
	(lshrsi3_zero_extend_2, lshrsi3_zero_extend_3): New.

	gcc/testsuite/
	* gcc.target/riscv/riscv.exp: New.
	* gcc.target/riscv/zero-extend-1.c: New.
	* gcc.target/riscv/zero-extend-2.c: New.
	* gcc.target/riscv/zero-extend-3.c: New.
	* gcc.target/riscv/zero-extend-4.c: New.


Co-Authored-By: Andrew Waterman <andrew@sifive.com>

From-SVN: r255257

gcc/cp/ChangeLog:
	* parser.c (cp_parser_unary_expression): Generate a location for
	"noexcept".
	(cp_parser_trait_expr): Generate and return a location_t,
	converting the return type from tree to cp_expr.
	(cp_parser_static_assert): Pass location of the condition to
	finish_static_assert, rather than that of the "static_assert"
	token, where available.

gcc/testsuite/ChangeLog:
	* g++.dg/cpp1y/static_assert3.C: New test case.

libstdc++-v3/ChangeLog:
	* testsuite/20_util/duration/literals/range.cc: Update expected
	line of a static_assert failure.

From-SVN: r255255

/cp
2017-11-29  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/82293
	* lambda.c (nonlambda_method_basetype): Don't use LAMBDA_TYPE_P
	on a null type.

/testsuite
2017-11-29  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/82293
	* g++.dg/cpp0x/lambda/lambda-ice24.C: New.

From-SVN: r255254

	* call.c (build_operator_new_call): Update *args if we add the
	align_arg.

From-SVN: r255253

[testsuite]

2017-11-29  Will Schmidt  <will_schmidt@vnet.ibm.com>

    * gcc.target/powerpc/fold-vec-ld-char.c: Add lxv insn to expected output.
    * gcc.target/powerpc/fold-vec-ld-double.c: Add lxv insn to expected output.
    * gcc.target/powerpc/fold-vec-ld-float.c: Add lxv insn to expected output.
    * gcc.target/powerpc/fold-vec-ld-int.c: Add lxv insn to expected output.
    * gcc.target/powerpc/fold-vec-ld-longlong.c: Add lxv insn to expected output.
    * gcc.target/powerpc/fold-vec-ld-short.c: Add lxv insn to expected output.

From-SVN: r255252

[testsuite]
2017-11-29  Will Schmidt  <will_schmidt@vnet.ibm.com>

    * gcc.target/powerpc/fold-vec-splat-8.c: Add vspltisb to expected output.
    * gcc.target/powerpc/fold-vec-splats-int.c: Add mtvsrws to expected output.
    * gcc.target/powerpc/fold-vec-splats-longlong.c: Add mtvsrdd to expected output.

From-SVN: r255251

gcc/
	* config/i386/avx512vbmi2intrin.h (_mm512_shldv_epi16,
	_mm512_mask_shldv_epi16, _mm512_maskz_shldv_epi16, _mm512_shldv_epi32,
	_mm512_mask_shldv_epi32, _mm512_maskz_shldv_epi32, _mm512_shldv_epi64,
	_mm512_mask_shldv_epi64, _mm512_maskz_shldv_epi64): New intrinsics.
	* config/i386/avx512vbmi2vlintrin.h (_mm256_shldv_epi16,
	_mm256_mask_shldv_epi16, _mm256_maskz_shldv_epi16, _mm256_shldv_epi32,
	_mm256_mask_shldv_epi32, _mm256_maskz_shldv_epi32, _mm256_shldv_epi64,
	_mm256_mask_shldv_epi64, _mm256_maskz_shldv_epi64, _mm_shldv_epi16,
	_mm_mask_shldv_epi16, _mm_maskz_shldv_epi16, _mm_shldv_epi32,
	_mm_mask_shldv_epi32, _mm_maskz_shldv_epi32, _mm_shldv_epi64,
	_mm_mask_shldv_epi64, _mm_maskz_shldv_epi64): Ditto.
	* config/i386/i386-builtin.def (__builtin_ia32_vpshldv_v32hi,
	__builtin_ia32_vpshldv_v32hi_mask, __builtin_ia32_vpshldv_v32hi_maskz,
	__builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask,
	__builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi,
	__builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz,
	__builtin_ia32_vpshldv_v16si, __builtin_ia32_vpshldv_v16si_mask,
	__builtin_ia32_vpshldv_v16si_maskz, __builtin_ia32_vpshldv_v8si,
	__builtin_ia32_vpshldv_v8si_mask, __builtin_ia32_vpshldv_v8si_maskz,
	__builtin_ia32_vpshldv_v4si, __builtin_ia32_vpshldv_v4si_mask,
	__builtin_ia32_vpshldv_v4si_maskz, __builtin_ia32_vpshldv_v8di,
	__builtin_ia32_vpshldv_v8di_mask, __builtin_ia32_vpshldv_v8di_maskz,
	__builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask,
	__builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di,
	__builtin_ia32_vpshldv_v2di_mask,
	__builtin_ia32_vpshldv_v2di_maskz): New builtins.
	* config/i386/sse.md (vpshldv_<mode>, vpshldv_<mode>_mask,
	vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): New patterns.

gcc/testsuite/
	* gcc.target/i386/avx512f-vpshldv-1.c: New test.
	* gcc.target/i386/avx512f-vpshldvd-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshldvq-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshldvw-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldv-1.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldvd-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldvq-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldvw-2.c: Ditto.

From-SVN: r255250

gcc/
	* config/i386/avx512vbmi2intrin.h (_mm512_shrdv_epi16,
	_mm512_mask_shrdv_epi16, _mm512_maskz_shrdv_epi16, _mm512_shrdv_epi32,
	_mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64,
	_mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64): New intrinsics.
	* config/i386/avx512vbmi2vlintrin.h (_mm256_shrdv_epi16,
	_mm256_mask_shrdv_epi16, _mm256_maskz_shrdv_epi16, _mm256_shrdv_epi32,
	_mm256_mask_shrdv_epi32, _mm256_maskz_shrdv_epi32, _mm256_shrdv_epi64,
	_mm256_mask_shrdv_epi64, _mm256_maskz_shrdv_epi64, _mm_shrdv_epi16,
	_mm_mask_shrdv_epi16, _mm_maskz_shrdv_epi16, _mm_shrdv_epi32,
	_mm_mask_shrdv_epi32, _mm_maskz_shrdv_epi32, _mm_shrdv_epi64,
	_mm_mask_shrdv_epi64, _mm_maskz_shrdv_epi64): Ditto.
	* config/i386/i386-builtin-types.def (V32HI_FTYPE_V32HI_V32HI_V32HI,
	V32HI_FTYPE_V32HI_V32HI_V32HI_INT, V16HI_FTYPE_V16HI_V16HI_V16HI_INT,
	V8HI_FTYPE_V8HI_V8HI_V8HI_INT, V8SI_FTYPE_V8SI_V8SI_V8SI_INT,
	V4SI_FTYPE_V4SI_V4SI_V4SI_INT, V8DI_FTYPE_V8DI_V8DI_V8DI,
	V8DI_FTYPE_V8DI_V8DI_V8DI_INT, V4DI_FTYPE_V4DI_V4DI_V4DI_INT,
	V16SI_FTYPE_V16SI_V16SI_V16SI, V16SI_FTYPE_V16SI_V16SI_V16SI_INT,
	V2DI_FTYPE_V2DI_V2DI_V2DI_INT): New types.
	* config/i386/i386.c (ix86_expand_args_builtin): Handle new types.
	* config/i386/sse.md (vpshrdv_<mode>, vpshrdv_<mode>_mask,
	vpshrdv_<mode>_maskz, vpshrdv_<mode>_maskz_1): New pattern.

gcc/testsuite/
	* gcc.target/i386/avx512f-vpshrdv-1.c: New test.
	* gcc.target/i386/avx512f-vpshrdvd-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshrdvq-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshrdvw-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshrdw-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshrdv-1.c: Ditto.
	* gcc.target/i386/avx512vl-vpshrdvd-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshrdvq-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshrdvw-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshrdw-2.c: Ditto.

From-SVN: r255249

From-SVN: r255248

	PR tree-optimization/83195
	* gcc.dg/pr82929.c: Don't check for "Merging successful" on arm.
	* gcc.dg/pr82929-2.c: New test.

From-SVN: r255247

Needed for the UT699 errata workaround to function correctly when
compiling with -fPIC.

2017-11-29  Daniel Cederman  <cederman@gaisler.com>

gcc/
	* config/sparc/sparc.c (sparc_do_work_around_errata): Treat the
        movsi_pic_gotdata_op instruction as a load for the UT699 errata
        workaround.

From-SVN: r255239

The sequence
  st
  fdivd / fsqrtd
  std
was generated in some cases with -mfix-ut699 when there was
a st before the div/sqrt. This sequence could trigger the b2bst errata.

Now the following safe sequence is generated instead:
  st
  nop
  fdivd / fsqrtd
  std

2017-11-29  Martin Aberg  <maberg@gaisler.com>

gcc/
	* config/sparc/sparc.md (divdf3_fix): Add NOP and adjust length
        to prevent b2bst errata sequence.
        (sqrtdf2_fix): Likewise.

From-SVN: r255238

This patch provides a workaround for the errata described in GRLIB-TN-0013.

If the workaround is enabled it will:

* Prevent div and sqrt instructions in the delay slot.

* Insert NOPs to prevent the sequence (div/sqrt) -> (two or three floating
  point operations or loads) -> (div/sqrt).

* Not insert NOPs if any of the floating point operations have a dependency
  on the destination register of the first (div/sqrt).

* Not insert NOPs if one of the floating point operations is a (div/sqrt).

* Insert NOPs to prevent (div/sqrt) followed by a branch.

It is applicable to GR712RC, UT700, and UT699.

2017-11-29  Daniel Cederman  <cederman@gaisler.com>

gcc/
	* config/sparc/sparc.c (fpop_reg_depend_p): New function.
	(div_sqrt_insn_p): New function.
	(sparc_do_work_around_errata): Insert NOP instructions to
	prevent sequences that could trigger the TN-0013 errata for
	certain LEON3 processors.
	(pass_work_around_errata::gate): Also test sparc_fix_lost_divsqrt.
	(sparc_option_override): Set sparc_fix_lost_divsqrt appropriately.
	* config/sparc/sparc.md (fix_lost_divsqrt): New attribute.
	(in_branch_delay): Prevent div and sqrt in delay slot if
	fix_lost_divsqrt.
	* config/sparc/sparc.opt (sparc_fix_lost_divsqrt): New variable.

From-SVN: r255237

This patch provides a workaround for the errata described in GRLIB-TN-0010.

If the workaround is enabled it will:

 * Insert a NOP between load instruction and atomic
   instruction (swap, ldstub, casa).

 * Insert a NOP at branch target if load in delay slot
   and atomic instruction at branch target.

It is applicable to UT700.

2017-11-29  Daniel Cederman  <cederman@gaisler.com>

gcc/
	* config/sparc/sparc.c (atomic_insn_p): New function.
	(sparc_do_work_around_errata): Insert NOP instructions to
	prevent sequences that could trigger the TN-0010 errata for
	UT700.
	* config/sparc/sync.md (atomic_compare_and_swap_leon3_1): Make
	instruction referable in atomic_insns_p.

From-SVN: r255236

This patch provides a workaround for the errata described in GRLIB-TN-0011.

If the workaround is enabled it will:

 * Insert .align 16 before atomic instructions (swap, ldstub, casa).

It is applicable to GR712RC.

2017-11-29  Daniel Cederman  <cederman@gaisler.com>

gcc/
	* config/sparc/sync.md (swapsi): 16-byte align if sparc_fix_gr712rc.
	(atomic_compare_and_swap_leon3_1): Likewise.
	(ldstub): Likewise.

From-SVN: r255235

This patch provides a workaround for the errata described in GRLIB-TN-0012.

If the workaround is enabled it will:

 * Prevent any floating-point operation from being placed in the
   delay slot of an annulled integer branch.

 * Place a NOP at the branch target of an integer branch if it is
   a floating-point operation or a floating-point branch.

It is applicable to GR712RC.

2017-11-29  Daniel Cederman  <cederman@gaisler.com>

gcc/
	* config/sparc/sparc.c (fpop_insn_p): New function.
	(sparc_do_work_around_errata): Insert NOP instructions to
	prevent sequences that could trigger the TN-0012 errata for
	GR712RC.
	(pass_work_around_errata::gate): Also test sparc_fix_gr712rc.
	* config/sparc/sparc.md (fix_gr712rc): New attribute.
	(in_branch_annul_delay): Prevent floating-point instructions
	in delay slot of annulled integer branch.

From-SVN: r255234

re PR tree-optimization/83202 (Try joining operations on consecutive array elements during tree vectorization)

2017-11-29  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/83202
	* tree-vect-slp.c (scalar_stmts_set_t): New typedef.
	(bst_fail): Use it.
	(vect_analyze_slp_cost_1): Add visited set, do not account SLP
	nodes vectorized to the same stmts multiple times.
	(vect_analyze_slp_cost): Allocate a visited set and pass it down.
	(vect_analyze_slp_instance): Adjust.
	(scalar_stmts_to_slp_tree_map_t): New typedef.
	(vect_schedule_slp_instance): Add a map recording the SLP node
	representing the vectorized stmts for a set of scalar stmts.
	Avoid code-generating redundancies.
	(vect_schedule_slp): Allocate map and pass it down.

	* gcc.dg/vect/costmodel/x86_64/costmodel-pr83202.c: New testcase.

From-SVN: r255233

From-SVN: r255232

https://gcc.gnu.org/ml/gcc-patches/2017-11/msg02453.html
	PR c++/83817
	* tree.c (build_complex_type): Fix canonicalization.  Only fill in
	type if it is new.

	PR c++/83187
	* g++.dg/opt/pr83187.C: New.

From-SVN: r255231

The recently added store_pair_lanes causes ICEs in output_operand.
This is due to aarch64_classify_address treating it like a 128-bit STR
rather than a STP.  The valid immediate offsets don't fully overlap,
causing it to return false.  Eg. offset 264 is a valid 8-byte STP offset
but not a valid 16-byte STR offset since it isn't a multiple of 16.

The original instruction isn't passed in the printing code, so the context
is unclear.  The solution is to add a new operand formatting specifier
which is used for LDP/STP instructions like this.  This, like the Uml
constraint that applies to store_pair_lanes, uses PARALLEL when calling
aarch64_classify_address so that it knows it is an STP.
Also add the 'z' specifier for future use by load/store pair instructions.

    gcc/
	* config/aarch64/aarch64.c (aarch64_print_operand): Add new
	cases for printing LDP/STP memory addresses.
	(aarch64_print_address_internal): Renamed from
	aarch64_print_operand_address, added parameter, add Pmode check.
	(aarch64_print_ldpstp_address): New function for LDP/STP addresses.
	(aarch64_print_operand_address): Indirect to
	aarch64_print_address_internal.
	* config/aarch64/aarch64-simd.md (store_pair_lanes): Use new
	'y' operand output specifier.

From-SVN: r255230

	PR middle-end/83185
	* tree.c (build_simple_mem_ref_loc): Handle
	get_addr_base_and_unit_offset returning a MEM_REF.

	* gcc.dg/asan/pr83185.c: New test.

From-SVN: r255229

	PR middle-end/80929
	* rtlanal.c (seq_cost): For non-single_set insns try to use insn_cost.

From-SVN: r255228

From-SVN: r255227

	PR target/80819
	* config/i386/sse.md (vec_concatv2di): Remove * from (=Yr,0,*rm)
	alternative.

	* gcc.target/i386/pr80819-1.c: New test.
	* gcc.target/i386/pr80819-2.c: New test.

From-SVN: r255226

2017-11-28  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

	PR libgfortran/83168
	* io/write.c (select_string): Bump size by one to avoid
	overrun.

From-SVN: r255225

From-SVN: r255224