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Commit 7c080ade by Jan Hubicka Committed by Jan Hubicka
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re PR target/81616 (Update -mtune=generic for the current Intel and AMD processors) 

	PR target/81616
	* x86-tnue-costs.h (generic_cost): Revise for modern CPUs
	* gcc.target/i386/l_fma_double_1.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_2.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_3.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_4.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_5.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_double_6.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_1.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_2.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_3.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_4.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_5.c: Update count of fma instructions.
	* gcc.target/i386/l_fma_float_6.c: Update count of fma instructions.

From-SVN: r255268
parent a52206ae
Showing with 81 additions and 60 deletions
gcc/ChangeLog
2017-11-30 Jan Hubicka <hubicka@ucw.cz>
PR target/81616
* x86-tnue-costs.h (generic_cost): Revise for modern CPUs
2017-11-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/83202
gcc/config/i386/x86-tune-costs.h
......@@ -2243,11 +2243,11 @@ struct processor_costs generic_cost = {
COSTS_N_INSNS (4), /* HI */
COSTS_N_INSNS (3), /* SI */
COSTS_N_INSNS (4), /* DI */
COSTS_N_INSNS (2)}, /* other */
COSTS_N_INSNS (4)}, /* other */
0, /* cost of multiply per each bit set */
{COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
COSTS_N_INSNS (26), /* HI */
COSTS_N_INSNS (42), /* SI */
{COSTS_N_INSNS (16), /* cost of a divide/mod for QI */
COSTS_N_INSNS (22), /* HI */
COSTS_N_INSNS (30), /* SI */
COSTS_N_INSNS (74), /* DI */
COSTS_N_INSNS (74)}, /* other */
COSTS_N_INSNS (1), /* cost of movsx */
......@@ -2275,13 +2275,13 @@ struct processor_costs generic_cost = {
2, 3, 4, /* cost of moving XMM,YMM,ZMM register */
{6, 6, 6, 10, 15}, /* cost of loading SSE registers
in 32,64,128,256 and 512-bit */
{10, 10, 10, 15, 20}, /* cost of unaligned loads. */
{6, 6, 6, 10, 15}, /* cost of unaligned loads. */
{6, 6, 6, 10, 15}, /* cost of storing SSE registers
in 32,64,128,256 and 512-bit */
{10, 10, 10, 15, 20}, /* cost of unaligned storess. */
20, 20, /* SSE->integer and integer->SSE moves */
6, 6, /* Gather load static, per_elt. */
6, 6, /* Gather store static, per_elt. */
{6, 6, 6, 10, 15}, /* cost of unaligned storess. */
6, 6, /* SSE->integer and integer->SSE moves */
18, 6, /* Gather load static, per_elt. */
18, 6, /* Gather store static, per_elt. */
32, /* size of l1 cache. */
512, /* size of l2 cache. */
64, /* size of prefetch block */
......@@ -2290,11 +2290,11 @@ struct processor_costs generic_cost = {
value is increased to perhaps more appropriate value of 5. */
3, /* Branch cost */
COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (3), /* cost of FMUL instruction. */
COSTS_N_INSNS (5), /* cost of FMUL instruction. */
COSTS_N_INSNS (20), /* cost of FDIV instruction. */
COSTS_N_INSNS (1), /* cost of FABS instruction. */
COSTS_N_INSNS (1), /* cost of FCHS instruction. */
COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
COSTS_N_INSNS (20), /* cost of FSQRT instruction. */
COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
......@@ -2306,7 +2306,7 @@ struct processor_costs generic_cost = {
COSTS_N_INSNS (32), /* cost of DIVSD instruction. */
COSTS_N_INSNS (30), /* cost of SQRTSS instruction. */
COSTS_N_INSNS (58), /* cost of SQRTSD instruction. */
1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */
1, 4, 3, 3, /* reassoc int, fp, vec_int, vec_fp. */
generic_memcpy,
generic_memset,
COSTS_N_INSNS (3), /* cond_taken_branch_cost. */
......
gcc/testsuite/ChangeLog
2017-11-30 Jan Hubicka <hubicka@ucw.cz>
PR target/81616
* gcc.target/i386/l_fma_double_1.c: Update count of fma instructions.
* gcc.target/i386/l_fma_double_2.c: Update count of fma instructions.
* gcc.target/i386/l_fma_double_3.c: Update count of fma instructions.
* gcc.target/i386/l_fma_double_4.c: Update count of fma instructions.
* gcc.target/i386/l_fma_double_5.c: Update count of fma instructions.
* gcc.target/i386/l_fma_double_6.c: Update count of fma instructions.
* gcc.target/i386/l_fma_float_1.c: Update count of fma instructions.
* gcc.target/i386/l_fma_float_2.c: Update count of fma instructions.
* gcc.target/i386/l_fma_float_3.c: Update count of fma instructions.
* gcc.target/i386/l_fma_float_4.c: Update count of fma instructions.
* gcc.target/i386/l_fma_float_5.c: Update count of fma instructions.
* gcc.target/i386/l_fma_float_6.c: Update count of fma instructions.
2017-11-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/83202
......
gcc/testsuite/gcc.target/i386/l_fma_double_1.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 32 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_2.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 32 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_3.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 32 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_4.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 32 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_5.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 32 } } */
gcc/testsuite/gcc.target/i386/l_fma_double_6.c
......@@ -13,7 +13,7 @@ typedef double adouble __attribute__((aligned(sizeof (double))));
/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 32 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 32 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_1.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 64 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_2.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 64 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_3.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 64 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_4.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 64 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_5.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 64 } } */
gcc/testsuite/gcc.target/i386/l_fma_float_6.c
......@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 64 } } */
/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 64 } } */
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