Skip to content

R
riscv-gcc-1
Commit 3d2aff3d by Julia Koval Committed by Kirill Yukhin
Options

nable VBMI2 support [7/7] 

gcc/
	* config/i386/avx512vbmi2intrin.h (_mm512_shldv_epi16,
	_mm512_mask_shldv_epi16, _mm512_maskz_shldv_epi16, _mm512_shldv_epi32,
	_mm512_mask_shldv_epi32, _mm512_maskz_shldv_epi32, _mm512_shldv_epi64,
	_mm512_mask_shldv_epi64, _mm512_maskz_shldv_epi64): New intrinsics.
	* config/i386/avx512vbmi2vlintrin.h (_mm256_shldv_epi16,
	_mm256_mask_shldv_epi16, _mm256_maskz_shldv_epi16, _mm256_shldv_epi32,
	_mm256_mask_shldv_epi32, _mm256_maskz_shldv_epi32, _mm256_shldv_epi64,
	_mm256_mask_shldv_epi64, _mm256_maskz_shldv_epi64, _mm_shldv_epi16,
	_mm_mask_shldv_epi16, _mm_maskz_shldv_epi16, _mm_shldv_epi32,
	_mm_mask_shldv_epi32, _mm_maskz_shldv_epi32, _mm_shldv_epi64,
	_mm_mask_shldv_epi64, _mm_maskz_shldv_epi64): Ditto.
	* config/i386/i386-builtin.def (__builtin_ia32_vpshldv_v32hi,
	__builtin_ia32_vpshldv_v32hi_mask, __builtin_ia32_vpshldv_v32hi_maskz,
	__builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask,
	__builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi,
	__builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz,
	__builtin_ia32_vpshldv_v16si, __builtin_ia32_vpshldv_v16si_mask,
	__builtin_ia32_vpshldv_v16si_maskz, __builtin_ia32_vpshldv_v8si,
	__builtin_ia32_vpshldv_v8si_mask, __builtin_ia32_vpshldv_v8si_maskz,
	__builtin_ia32_vpshldv_v4si, __builtin_ia32_vpshldv_v4si_mask,
	__builtin_ia32_vpshldv_v4si_maskz, __builtin_ia32_vpshldv_v8di,
	__builtin_ia32_vpshldv_v8di_mask, __builtin_ia32_vpshldv_v8di_maskz,
	__builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask,
	__builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di,
	__builtin_ia32_vpshldv_v2di_mask,
	__builtin_ia32_vpshldv_v2di_maskz): New builtins.
	* config/i386/sse.md (vpshldv_<mode>, vpshldv_<mode>_mask,
	vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): New patterns.

gcc/testsuite/
	* gcc.target/i386/avx512f-vpshldv-1.c: New test.
	* gcc.target/i386/avx512f-vpshldvd-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshldvq-2.c: Ditto.
	* gcc.target/i386/avx512f-vpshldvw-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldv-1.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldvd-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldvq-2.c: Ditto.
	* gcc.target/i386/avx512vl-vpshldvw-2.c: Ditto.

From-SVN: r255250
parent 8d4f237b
Showing with 663 additions and 0 deletions
gcc/ChangeLog
2017-11-29 Julia Koval <julia.koval@intel.com>
* config/i386/avx512vbmi2intrin.h (_mm512_shldv_epi16,
_mm512_mask_shldv_epi16, _mm512_maskz_shldv_epi16, _mm512_shldv_epi32,
_mm512_mask_shldv_epi32, _mm512_maskz_shldv_epi32, _mm512_shldv_epi64,
_mm512_mask_shldv_epi64, _mm512_maskz_shldv_epi64): New intrinsics.
* config/i386/avx512vbmi2vlintrin.h (_mm256_shldv_epi16,
_mm256_mask_shldv_epi16, _mm256_maskz_shldv_epi16, _mm256_shldv_epi32,
_mm256_mask_shldv_epi32, _mm256_maskz_shldv_epi32, _mm256_shldv_epi64,
_mm256_mask_shldv_epi64, _mm256_maskz_shldv_epi64, _mm_shldv_epi16,
_mm_mask_shldv_epi16, _mm_maskz_shldv_epi16, _mm_shldv_epi32,
_mm_mask_shldv_epi32, _mm_maskz_shldv_epi32, _mm_shldv_epi64,
_mm_mask_shldv_epi64, _mm_maskz_shldv_epi64): Ditto.
* config/i386/i386-builtin.def (__builtin_ia32_vpshldv_v32hi,
__builtin_ia32_vpshldv_v32hi_mask, __builtin_ia32_vpshldv_v32hi_maskz,
__builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask,
__builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi,
__builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz,
__builtin_ia32_vpshldv_v16si, __builtin_ia32_vpshldv_v16si_mask,
__builtin_ia32_vpshldv_v16si_maskz, __builtin_ia32_vpshldv_v8si,
__builtin_ia32_vpshldv_v8si_mask, __builtin_ia32_vpshldv_v8si_maskz,
__builtin_ia32_vpshldv_v4si, __builtin_ia32_vpshldv_v4si_mask,
__builtin_ia32_vpshldv_v4si_maskz, __builtin_ia32_vpshldv_v8di,
__builtin_ia32_vpshldv_v8di_mask, __builtin_ia32_vpshldv_v8di_maskz,
__builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask,
__builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di,
__builtin_ia32_vpshldv_v2di_mask,
__builtin_ia32_vpshldv_v2di_maskz): New builtins.
* config/i386/sse.md (vpshldv_<mode>, vpshldv_<mode>_mask,
vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): New patterns.
2017-11-29 Julia Koval <julia.koval@intel.com>
* config/i386/avx512vbmi2intrin.h (_mm512_shrdv_epi16,
_mm512_mask_shrdv_epi16, _mm512_maskz_shrdv_epi16, _mm512_shrdv_epi32,
_mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64,
gcc/config/i386/avx512vbmi2intrin.h
......@@ -432,7 +432,77 @@ _mm512_maskz_shrdv_epi64 (__mmask8 __A, __m512i __B, __m512i __C, __m512i __D)
return (__m512i)__builtin_ia32_vpshrdv_v8di_maskz ((__v8di)__B, (__v8di) __C,
(__v8di) __D, (__mmask8)__A);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_shldv_epi16 (__m512i __A, __m512i __B, __m512i __C)
{
return (__m512i) __builtin_ia32_vpshldv_v32hi ((__v32hi)__A, (__v32hi) __B,
(__v32hi) __C);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_shldv_epi16 (__m512i __A, __mmask32 __B, __m512i __C, __m512i __D)
{
return (__m512i)__builtin_ia32_vpshldv_v32hi_mask ((__v32hi)__A,
(__v32hi) __C, (__v32hi) __D, (__mmask32)__B);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_shldv_epi16 (__mmask32 __A, __m512i __B, __m512i __C, __m512i __D)
{
return (__m512i)__builtin_ia32_vpshldv_v32hi_maskz ((__v32hi)__B,
(__v32hi) __C, (__v32hi) __D, (__mmask32)__A);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_shldv_epi32 (__m512i __A, __m512i __B, __m512i __C)
{
return (__m512i) __builtin_ia32_vpshldv_v16si ((__v16si)__A, (__v16si) __B,
(__v16si) __C);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_shldv_epi32 (__m512i __A, __mmask16 __B, __m512i __C, __m512i __D)
{
return (__m512i)__builtin_ia32_vpshldv_v16si_mask ((__v16si)__A,
(__v16si) __C, (__v16si) __D, (__mmask16)__B);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_shldv_epi32 (__mmask16 __A, __m512i __B, __m512i __C, __m512i __D)
{
return (__m512i)__builtin_ia32_vpshldv_v16si_maskz ((__v16si)__B,
(__v16si) __C, (__v16si) __D, (__mmask16)__A);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_shldv_epi64 (__m512i __A, __m512i __B, __m512i __C)
{
return (__m512i) __builtin_ia32_vpshldv_v8di ((__v8di)__A, (__v8di) __B,
(__v8di) __C);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_shldv_epi64 (__m512i __A, __mmask8 __B, __m512i __C, __m512i __D)
{
return (__m512i)__builtin_ia32_vpshldv_v8di_mask ((__v8di)__A, (__v8di) __C,
(__v8di) __D, (__mmask8)__B);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_shldv_epi64 (__mmask8 __A, __m512i __B, __m512i __C, __m512i __D)
{
return (__m512i)__builtin_ia32_vpshldv_v8di_maskz ((__v8di)__B, (__v8di) __C,
(__v8di) __D, (__mmask8)__A);
}
#ifdef __DISABLE_AVX512VBMI2BW__
#undef __DISABLE_AVX512VBMI2BW__
......
gcc/config/i386/avx512vbmi2vlintrin.h
......@@ -762,6 +762,151 @@ _mm_maskz_shrdv_epi64 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D)
(__v2di) __D, (__mmask8)__A);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_shldv_epi16 (__m256i __A, __m256i __B, __m256i __C)
{
return (__m256i) __builtin_ia32_vpshldv_v16hi ((__v16hi)__A, (__v16hi) __B,
(__v16hi) __C);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_shldv_epi16 (__m256i __A, __mmask16 __B, __m256i __C, __m256i __D)
{
return (__m256i)__builtin_ia32_vpshldv_v16hi_mask ((__v16hi)__A,
(__v16hi) __C, (__v16hi) __D, (__mmask16)__B);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_shldv_epi16 (__mmask16 __A, __m256i __B, __m256i __C, __m256i __D)
{
return (__m256i)__builtin_ia32_vpshldv_v16hi_maskz ((__v16hi)__B,
(__v16hi) __C, (__v16hi) __D, (__mmask16)__A);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_shldv_epi32 (__m256i __A, __m256i __B, __m256i __C)
{
return (__m256i) __builtin_ia32_vpshldv_v8si ((__v8si)__A, (__v8si) __B,
(__v8si) __C);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_shldv_epi32 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D)
{
return (__m256i)__builtin_ia32_vpshldv_v8si_mask ((__v8si)__A, (__v8si) __C,
(__v8si) __D, (__mmask8)__B) ;
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_shldv_epi32 (__mmask8 __A, __m256i __B, __m256i __C, __m256i __D)
{
return (__m256i)__builtin_ia32_vpshldv_v8si_maskz ((__v8si)__B, (__v8si) __C,
(__v8si) __D, (__mmask8)__A);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_shldv_epi64 (__m256i __A, __m256i __B, __m256i __C)
{
return (__m256i) __builtin_ia32_vpshldv_v4di ((__v4di)__A, (__v4di) __B,
(__v4di) __C);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_shldv_epi64 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D)
{
return (__m256i)__builtin_ia32_vpshldv_v4di_mask ((__v4di)__A, (__v4di) __C,
(__v4di) __D, (__mmask8)__B);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_shldv_epi64 (__mmask8 __A, __m256i __B, __m256i __C, __m256i __D)
{
return (__m256i)__builtin_ia32_vpshldv_v4di_maskz ((__v4di)__B, (__v4di) __C,
(__v4di) __D, (__mmask8)__A);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_shldv_epi16 (__m128i __A, __m128i __B, __m128i __C)
{
return (__m128i) __builtin_ia32_vpshldv_v8hi ((__v8hi)__A, (__v8hi) __B,
(__v8hi) __C);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_mask_shldv_epi16 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D)
{
return (__m128i)__builtin_ia32_vpshldv_v8hi_mask ((__v8hi)__A, (__v8hi) __C,
(__v8hi) __D, (__mmask8)__B);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_maskz_shldv_epi16 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D)
{
return (__m128i)__builtin_ia32_vpshldv_v8hi_maskz ((__v8hi)__B, (__v8hi) __C,
(__v8hi) __D, (__mmask8)__A);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_shldv_epi32 (__m128i __A, __m128i __B, __m128i __C)
{
return (__m128i) __builtin_ia32_vpshldv_v4si ((__v4si)__A, (__v4si) __B,
(__v4si) __C);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_mask_shldv_epi32 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D)
{
return (__m128i)__builtin_ia32_vpshldv_v4si_mask ((__v4si)__A, (__v4si) __C,
(__v4si) __D, (__mmask8)__B);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_maskz_shldv_epi32 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D)
{
return (__m128i)__builtin_ia32_vpshldv_v4si_maskz ((__v4si)__B, (__v4si) __C,
(__v4si) __D, (__mmask8)__A);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_shldv_epi64 (__m128i __A, __m128i __B, __m128i __C)
{
return (__m128i) __builtin_ia32_vpshldv_v2di ((__v2di)__A, (__v2di) __B,
(__v2di) __C);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_mask_shldv_epi64 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D)
{
return (__m128i)__builtin_ia32_vpshldv_v2di_mask ((__v2di)__A, (__v2di) __C,
(__v2di) __D, (__mmask8)__B);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_maskz_shldv_epi64 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D)
{
return (__m128i)__builtin_ia32_vpshldv_v2di_maskz ((__v2di)__B, (__v2di) __C,
(__v2di) __D, (__mmask8)__A);
}
#ifdef __DISABLE_AVX512VBMI2VL__
......
gcc/config/i386/i386-builtin.def
......@@ -2693,6 +2693,34 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di, "__builtin_ia32_vpshr
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di_mask, "__builtin_ia32_vpshrdv_v2di_mask", IX86_BUILTIN_VPSHRDVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di_maskz, "__builtin_ia32_vpshrdv_v2di_maskz", IX86_BUILTIN_VPSHRDVV2DI_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v32hi, "__builtin_ia32_vpshldv_v32hi", IX86_BUILTIN_VPSHLDVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v32hi_mask, "__builtin_ia32_vpshldv_v32hi_mask", IX86_BUILTIN_VPSHLDVV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v32hi_maskz, "__builtin_ia32_vpshldv_v32hi_maskz", IX86_BUILTIN_VPSHLDVV32HI_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16hi, "__builtin_ia32_vpshldv_v16hi", IX86_BUILTIN_VPSHLDVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16hi_mask, "__builtin_ia32_vpshldv_v16hi_mask", IX86_BUILTIN_VPSHLDVV16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16hi_maskz, "__builtin_ia32_vpshldv_v16hi_maskz", IX86_BUILTIN_VPSHLDVV16HI_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8hi, "__builtin_ia32_vpshldv_v8hi", IX86_BUILTIN_VPSHLDVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8hi_mask, "__builtin_ia32_vpshldv_v8hi_mask", IX86_BUILTIN_VPSHLDVV8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8hi_maskz, "__builtin_ia32_vpshldv_v8hi_maskz", IX86_BUILTIN_VPSHLDVV8HI_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16si, "__builtin_ia32_vpshldv_v16si", IX86_BUILTIN_VPSHLDVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16si_mask, "__builtin_ia32_vpshldv_v16si_mask", IX86_BUILTIN_VPSHLDVV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16si_maskz, "__builtin_ia32_vpshldv_v16si_maskz", IX86_BUILTIN_VPSHLDVV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8si, "__builtin_ia32_vpshldv_v8si", IX86_BUILTIN_VPSHLDVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8si_mask, "__builtin_ia32_vpshldv_v8si_mask", IX86_BUILTIN_VPSHLDVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8si_maskz, "__builtin_ia32_vpshldv_v8si_maskz", IX86_BUILTIN_VPSHLDVV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4si, "__builtin_ia32_vpshldv_v4si", IX86_BUILTIN_VPSHLDVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4si_mask, "__builtin_ia32_vpshldv_v4si_mask", IX86_BUILTIN_VPSHLDVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4si_maskz, "__builtin_ia32_vpshldv_v4si_maskz", IX86_BUILTIN_VPSHLDVV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8di, "__builtin_ia32_vpshldv_v8di", IX86_BUILTIN_VPSHLDVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8di_mask, "__builtin_ia32_vpshldv_v8di_mask", IX86_BUILTIN_VPSHLDVV8DI_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8di_maskz, "__builtin_ia32_vpshldv_v8di_maskz", IX86_BUILTIN_VPSHLDVV8DI_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4di, "__builtin_ia32_vpshldv_v4di", IX86_BUILTIN_VPSHLDVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4di_mask, "__builtin_ia32_vpshldv_v4di_mask", IX86_BUILTIN_VPSHLDVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4di_maskz, "__builtin_ia32_vpshldv_v4di_maskz", IX86_BUILTIN_VPSHLDVV4DI_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di, "__builtin_ia32_vpshldv_v2di", IX86_BUILTIN_VPSHLDVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di_mask, "__builtin_ia32_vpshldv_v2di_mask", IX86_BUILTIN_VPSHLDVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT)
BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di_maskz, "__builtin_ia32_vpshldv_v2di_maskz", IX86_BUILTIN_VPSHLDVV2DI_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT)
BDESC_END (ARGS2, SPECIAL_ARGS2)
BDESC_FIRST (special_args2, SPECIAL_ARGS2, OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_compressstorev64qi_mask, "__builtin_ia32_compressstoreuqi512_mask", IX86_BUILTIN_PCOMPRESSBSTORE512, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_UDI)
......
gcc/config/i386/sse.md
......@@ -165,6 +165,7 @@
UNSPEC_VPSHLD
UNSPEC_VPSHRD
UNSPEC_VPSHRDV
UNSPEC_VPSHLDV
])
(define_c_enum "unspecv" [
......@@ -20171,3 +20172,59 @@
"vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
[(set_attr ("prefix") ("evex"))
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshldv_<mode>"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
(unspec:VI248_VLBW
[(match_operand:VI248_VLBW 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
] UNSPEC_VPSHLDV))]
"TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
[(set_attr ("prefix") ("evex"))
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshldv_<mode>_mask"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
(vec_merge:VI248_VLBW (unspec:VI248_VLBW
[(match_operand:VI248_VLBW 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
] UNSPEC_VPSHLDV)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
)]
"TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
[(set_attr ("prefix") ("evex"))
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vpshldv_<mode>_maskz"
[(match_operand:VI248_VLBW 0 "register_operand")
(match_operand:VI248_VLBW 1 "register_operand")
(match_operand:VI248_VLBW 2 "register_operand")
(match_operand:VI248_VLBW 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI2"
{
emit_insn (gen_vpshldv_<mode>_maskz_1 (
operands[0], operands[1], operands[2], operands[3],
CONST0_RTX (<MODE>mode), operands[4]));
DONE;
})
(define_insn "vpshldv_<mode>_maskz_1"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
(vec_merge:VI248_VLBW (unspec:VI248_VLBW
[(match_operand:VI248_VLBW 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
] UNSPEC_VPSHLDV)
(match_operand:VI248_VLBW 4 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
)]
"TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
[(set_attr ("prefix") ("evex"))
(set_attr "mode" "<sseinsnmode>")])
gcc/testsuite/ChangeLog
2017-11-29 Julia Koval <julia.koval@intel.com>
* gcc.target/i386/avx512f-vpshldv-1.c: New test.
* gcc.target/i386/avx512f-vpshldvd-2.c: Ditto.
* gcc.target/i386/avx512f-vpshldvq-2.c: Ditto.
* gcc.target/i386/avx512f-vpshldvw-2.c: Ditto.
* gcc.target/i386/avx512vl-vpshldv-1.c: Ditto.
* gcc.target/i386/avx512vl-vpshldvd-2.c: Ditto.
* gcc.target/i386/avx512vl-vpshldvq-2.c: Ditto.
* gcc.target/i386/avx512vl-vpshldvw-2.c: Ditto.
2017-11-29 Julia Koval <julia.koval@intel.com>
* gcc.target/i386/avx512f-vpshrdv-1.c: New test.
* gcc.target/i386/avx512f-vpshrdvd-2.c: Ditto.
* gcc.target/i386/avx512f-vpshrdvq-2.c: Ditto.
......
gcc/testsuite/gcc.target/i386/avx512f-vpshldv-1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-mavx512f -mavx512vbmi2 -mavx512bw -O2" } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m512i x,y,z,z1;
volatile __mmask32 m32;
volatile __mmask16 m16;
volatile __mmask8 m8;
void extern
avx512f_test (void)
{
x = _mm512_shldv_epi16 (x, y, z);
x = _mm512_mask_shldv_epi16 (x, m32, y, z);
x = _mm512_maskz_shldv_epi16 (m32, x, y, z);
x = _mm512_shldv_epi32 (x, y, z);
x = _mm512_mask_shldv_epi32 (x, m16, y, z);
x = _mm512_maskz_shldv_epi32 (m16, x, y, z);
x = _mm512_shldv_epi64 (x, y, z);
x = _mm512_mask_shldv_epi64 (x, m8, y, z);
x = _mm512_maskz_shldv_epi64 (m8, x, y, z);
}
gcc/testsuite/gcc.target/i386/avx512f-vpshldvd-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512f -mavx512vbmi2 -mavx512bw" } */
/* { dg-require-effective-target avx512f } */
/* { dg-require-effective-target avx512vbmi2 } */
#define AVX512F
#define AVX512VBMI2
#include "avx512f-helper.h"
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
static void
CALC (int *r, int *dst, int *s1, int *s2)
{
int i;
for (i = 0; i < SIZE; i++)
{
r[i] = (dst[i] << (s2[i] & 31)) | (s1[i] >> (32 - (s2[i] & 31)));
}
}
void
TEST (void)
{
int i;
UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
MASK_TYPE mask = MASK_VALUE;
int res_ref[SIZE];
for (i = 0; i < SIZE; i++)
{
src1.a[i] = 2 + i;
src2.a[i] = 1 + 3*i;
}
for (i = 0; i < SIZE; i++)
{
res1.a[i] = DEFAULT_VALUE;
res2.a[i] = DEFAULT_VALUE;
res3.a[i] = DEFAULT_VALUE;
}
CALC (res_ref, res1.a, src1.a, src2.a);
res1.x = INTRINSIC (_shldv_epi32) (res1.x, src1.x, src2.x);
res2.x = INTRINSIC (_mask_shldv_epi32) (res2.x, mask, src1.x, src2.x);
res3.x = INTRINSIC (_maskz_shldv_epi32) (mask, res3.x, src1.x, src2.x);
if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
abort ();
MASK_MERGE (i_d) (res_ref, mask, SIZE);
if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
abort ();
MASK_ZERO (i_d) (res_ref, mask, SIZE);
if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
abort ();
}
gcc/testsuite/gcc.target/i386/avx512f-vpshldvq-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512f -mavx512vbmi2 -mavx512bw" } */
/* { dg-require-effective-target avx512f } */
/* { dg-require-effective-target avx512vbmi2 } */
#define AVX512F
#define AVX512VBMI2
#include "avx512f-helper.h"
#define SIZE (AVX512F_LEN / 64)
#include "avx512f-mask-type.h"
static void
CALC (unsigned long long *r, unsigned long long *dst, unsigned long long *s1, unsigned long long *s2)
{
int i;
for (i = 0; i < SIZE; i++)
{
r[i] = (dst[i] << (s2[i] & 63)) | (s1[i] >> (64 - (s2[i] & 63)));
}
}
void
TEST (void)
{
int i;
UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
MASK_TYPE mask = MASK_VALUE;
unsigned long long res_ref[SIZE];
for (i = 0; i < SIZE; i++)
{
src1.a[i] = 2 + i;
src2.a[i] = 1 + 3*i;
}
for (i = 0; i < SIZE; i++)
{
res1.a[i] = DEFAULT_VALUE;
res2.a[i] = DEFAULT_VALUE;
res3.a[i] = DEFAULT_VALUE;
}
CALC (res_ref, res1.a, src1.a, src2.a);
res1.x = INTRINSIC (_shldv_epi64) (res1.x, src1.x, src2.x);
res2.x = INTRINSIC (_mask_shldv_epi64) (res2.x, mask, src1.x, src2.x);
res3.x = INTRINSIC (_maskz_shldv_epi64) (mask, res3.x, src1.x, src2.x);
if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
abort ();
MASK_MERGE (i_q) (res_ref, mask, SIZE);
if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
abort ();
MASK_ZERO (i_q) (res_ref, mask, SIZE);
if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
abort ();
}
gcc/testsuite/gcc.target/i386/avx512f-vpshldvw-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512f -mavx512vbmi2 -mavx512bw" } */
/* { dg-require-effective-target avx512f } */
/* { dg-require-effective-target avx512vbmi2 } */
#define AVX512F
#define AVX512VBMI2
#include "avx512f-helper.h"
#define SIZE (AVX512F_LEN / 16)
#include "avx512f-mask-type.h"
static void
CALC (short *r, short *dst, short *s1, short *s2)
{
int i;
for (i = 0; i < SIZE; i++)
{
r[i] = (dst[i] << (s2[i] & 15)) | (s1[i] >> (16 - (s2[i] & 15)));
}
}
void
TEST (void)
{
int i;
UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3, src1, src2;
MASK_TYPE mask = MASK_VALUE;
short res_ref[SIZE];
for (i = 0; i < SIZE; i++)
{
src1.a[i] = 2 + i;
src2.a[i] = 1 + 3*i;
}
for (i = 0; i < SIZE; i++)
{
res1.a[i] = DEFAULT_VALUE;
res2.a[i] = DEFAULT_VALUE;
res3.a[i] = DEFAULT_VALUE;
}
CALC (res_ref, res1.a, src1.a, src2.a);
res1.x = INTRINSIC (_shldv_epi16) (res1.x, src1.x, src2.x);
res2.x = INTRINSIC (_mask_shldv_epi16) (res2.x, mask, src1.x, src2.x);
res3.x = INTRINSIC (_maskz_shldv_epi16) (mask, res3.x, src1.x, src2.x);
if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref))
abort ();
MASK_MERGE (i_w) (res_ref, mask, SIZE);
if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref))
abort ();
MASK_ZERO (i_w) (res_ref, mask, SIZE);
if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref))
abort ();
}
gcc/testsuite/gcc.target/i386/avx512vl-vpshldv-1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-mavx512vl -mavx512vbmi2 -mavx512bw -O2" } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpshldvq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m256i x,y,z;
volatile __m128i x_,y_,z_;
volatile __mmask32 m;
void extern
avx512f_test (void)
{
x = _mm256_shldv_epi16 (x, y, z);
x = _mm256_mask_shldv_epi16 (x, m, y, z);
x = _mm256_maskz_shldv_epi16 (m, x, y, z);
x = _mm256_shldv_epi32 (x, y, z);
x = _mm256_mask_shldv_epi32 (x, m, y, z);
x = _mm256_maskz_shldv_epi32 (m, x, y, z);
x = _mm256_shldv_epi64 (x, y, z);
x = _mm256_mask_shldv_epi64 (x, m, y, z);
x = _mm256_maskz_shldv_epi64 (m, x, y, z);
x_ = _mm_shldv_epi16 (x_, y_, z_);
x_ = _mm_mask_shldv_epi16 (x_, m, y_, z_);
x_ = _mm_maskz_shldv_epi16 (m, x_, y_, z_);
x_ = _mm_shldv_epi32 (x_, y_, z_);
x_ = _mm_mask_shldv_epi32 (x_, m, y_, z_);
x_ = _mm_maskz_shldv_epi32 (m, x_, y_, z_);
x_ = _mm_shldv_epi64 (x_, y_, z_);
x_ = _mm_mask_shldv_epi64 (x_, m, y_, z_);
x_ = _mm_maskz_shldv_epi64 (m, x_, y_, z_);
}
gcc/testsuite/gcc.target/i386/avx512vl-vpshldvd-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512vl -mavx512vbmi2 -mavx512bw" } */
/* { dg-require-effective-target avx512vl } */
/* { dg-require-effective-target avx512vbmi2 } */
#define AVX512VL
#define AVX512F_LEN 256
#define AVX512F_LEN_HALF 128
#include "avx512f-vpshldvd-2.c"
#undef AVX512F_LEN
#undef AVX512F_LEN_HALF
#define AVX512F_LEN 128
#define AVX512F_LEN_HALF 128
#include "avx512f-vpshldvd-2.c"
gcc/testsuite/gcc.target/i386/avx512vl-vpshldvq-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512vl -mavx512vbmi2 -mavx512bw" } */
/* { dg-require-effective-target avx512vl } */
/* { dg-require-effective-target avx512vbmi2 } */
#define AVX512VL
#define AVX512F_LEN 256
#define AVX512F_LEN_HALF 128
#include "avx512f-vpshldvq-2.c"
#undef AVX512F_LEN
#undef AVX512F_LEN_HALF
#define AVX512F_LEN 128
#define AVX512F_LEN_HALF 128
#include "avx512f-vpshldvq-2.c"
gcc/testsuite/gcc.target/i386/avx512vl-vpshldvw-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512vl -mavx512vbmi2 -mavx512bw" } */
/* { dg-require-effective-target avx512vl } */
/* { dg-require-effective-target avx512vbmi2 } */
#define AVX512VL
#define AVX512F_LEN 256
#define AVX512F_LEN_HALF 128
#include "avx512f-vpshldvw-2.c"
#undef AVX512F_LEN
#undef AVX512F_LEN_HALF
#define AVX512F_LEN 128
#define AVX512F_LEN_HALF 128
#include "avx512f-vpshldvw-2.c"
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment