2018-01-17  Steve Ellcey  <sellcey@cavium.com>

	* config/aarch64/aarch64.c (cgraph.h): New include.
	(intl.h): New include.
	(supported_simd_type): New function.
	(currently_supported_simd_type): Ditto.
	(aarch64_simd_clone_compute_vecsize_and_simdlen): Ditto.
	(aarch64_simd_clone_adjust): Ditto.
	(aarch64_simd_clone_usable): Ditto.
	(TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): New macro.
	(TARGET_SIMD_CLONE_ADJUST): Ditto.
	(TARGET_SIMD_CLONE_USABLE): Ditto.
	* config/i386/i386.c (ix86_simd_clone_adjust): Add definition check.
	* omp-simd-clone.c (expand_simd_clones): Add targetm.simd_clone.adjust
	call.

From-SVN: r268044

This patch contains the major part of the GCN back-end.  The machine
description has been broken out to avoid the mailing list size limit.

The back-end contains various bits that support OpenACC and OpenMP, but the
middle-end and libgomp patches are missing, as is mkoffload.  I include them
here because they're harmless and carving up the files seems like unnecessary
effort.  The remaining offload support will be posted at a later date.

The gcn-run.c is a separate tool that can run a GCN program on a GPU using
the ROCm drivers and HSA runtime libraries.

2019-01-17  Andrew Stubbs  <ams@codesourcery.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Tom de Vries  <tom@codesourcery.com>
	    Jan Hubicka  <hubicka@ucw.cz>
	    Martin Jambor  <mjambor@suse.cz>

	gcc/
	* common/config/gcn/gcn-common.c: New file.
	* config/gcn/driver-gcn.c: New file.
	* config/gcn/gcn-builtins.def: New file.
	* config/gcn/gcn-hsa.h: New file.
	* config/gcn/gcn-modes.def: New file.
	* config/gcn/gcn-opts.h: New file.
	* config/gcn/gcn-passes.def: New file.
	* config/gcn/gcn-protos.h: New file.
	* config/gcn/gcn-run.c: New file.
	* config/gcn/gcn-tree.c: New file.
	* config/gcn/gcn.c: New file.
	* config/gcn/gcn.h: New file.
	* config/gcn/gcn.opt: New file.
	* config/gcn/t-gcn-hsa: New file.


Co-Authored-By: Jan Hubicka <hubicka@ucw.cz>
Co-Authored-By: Julian Brown <julian@codesourcery.com>
Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Martin Jambor <mjambor@suse.cz>
Co-Authored-By: Tom de Vries <tom@codesourcery.com>

From-SVN: r268023

This patch contains the machine description portion of the GCN back-end.  I've
broken it out mainly to avoid the mailing list size limit.

2019-01-17  Andrew Stubbs  <ams@codesourcery.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Tom de Vries  <tom@codesourcery.com>
	    Jan Hubicka  <hubicka@ucw.cz>
	    Martin Jambor  <mjambor@suse.cz>

	gcc/
	* config/gcn/constraints.md: New file.
	* config/gcn/gcn-valu.md: New file.
	* config/gcn/gcn.md: New file.
	* config/gcn/predicates.md: New file.


Co-Authored-By: Jan Hubicka <hubicka@ucw.cz>
Co-Authored-By: Julian Brown <julian@codesourcery.com>
Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Martin Jambor <mjambor@suse.cz>
Co-Authored-By: Tom de Vries <tom@codesourcery.com>

From-SVN: r268022

gcc/ChangeLog:

	PR target/88851
	* config/aarch64/aarch64.md (STACK_CLASH_SVE_CFA_REGNUM): New.
	* config/aarch64/aarch64.c (aarch64_allocate_and_probe_stack_space): Use
	it and document registers.

gcc/testsuite/ChangeLog:

	PR target/88851
	* gcc.target/aarch64/stack-check-cfa-3.c: Update test.

From-SVN: r268017

This patch adds a tuning struct for the Arm Ares CPU and uses it for -m{cpu,tune}=ares.
The tunings are an initial attempt and may be improved upon in the future, but they serve
as a decent starting point for GCC 9.

With this I see a 1.3% improvement on SPEC2006 int and 0.3% on SPEC2006 fp with -mcpu=ares.
On SPEC2017 I see a 0.6% improvement in intrate and changes in the noise for fprate.

        * config/aarch64/aarch64.c (ares_tunings): Define.
        * config/aarch64/aarch64-cores.def (ares): Use the above.

From-SVN: r268015

gcc/ChangeLog
2019-01-17  Wei Xiao  <wei3.xiao@intel.com>

	PR target/88794
	Revert:

	2018-11-06  Wei Xiao  <wei3.xiao@intel.com>

	* config/i386/avx512fintrin.h: Update VFIXUPIMM* intrinsics.
	(_mm512_fixupimm_round_pd): Update parameters and builtin.
	(_mm512_maskz_fixupimm_round_pd): Ditto.
	(_mm512_fixupimm_round_ps): Ditto.
	(_mm512_maskz_fixupimm_round_ps): Ditto.
	(_mm_fixupimm_round_sd): Ditto.
	(_mm_maskz_fixupimm_round_sd): Ditto.
	(_mm_fixupimm_round_ss): Ditto.
	(_mm_maskz_fixupimm_round_ss): Ditto.
	(_mm512_fixupimm_pd): Ditto.
	(_mm512_maskz_fixupimm_pd): Ditto.
	(_mm512_fixupimm_ps): Ditto.
	(_mm512_maskz_fixupimm_ps): Ditto.
	(_mm_fixupimm_sd): Ditto.
	(_mm_maskz_fixupimm_sd): Ditto.
	(_mm_fixupimm_ss): Ditto.
	(_mm_maskz_fixupimm_ss): Ditto.
	(_mm512_mask_fixupimm_round_pd): Update builtin.
	(_mm512_mask_fixupimm_round_ps): Ditto.
	(_mm_mask_fixupimm_round_sd): Ditto.
	(_mm_mask_fixupimm_round_ss): Ditto.
	(_mm512_mask_fixupimm_pd): Ditto.
	(_mm512_mask_fixupimm_ps): Ditto.
	(_mm_mask_fixupimm_sd): Ditto.
	(_mm_mask_fixupimm_ss): Ditto.
	* config/i386/avx512vlintrin.h:
	(_mm256_fixupimm_pd): Update parameters and builtin.
	(_mm256_maskz_fixupimm_pd): Ditto.
	(_mm256_fixupimm_ps): Ditto.
	(_mm256_maskz_fixupimm_ps): Ditto.
	(_mm_fixupimm_pd): Ditto.
	(_mm_maskz_fixupimm_pd): Ditto.
	(_mm_fixupimm_ps): Ditto.
	(_mm_maskz_fixupimm_ps): Ditto.
	(_mm256_mask_fixupimm_pd): Update builtin.
	(_mm256_mask_fixupimm_ps): Ditto.
	(_mm_mask_fixupimm_pd): Ditto.
	(_mm_mask_fixupimm_ps): Ditto.
	* config/i386/i386-builtin-types.def: Add new types and remove useless ones.
	* config/i386/i386-builtin.def: Update builtin definitions.
	* config/i386/i386.c: Handle new builtin types and remove useless ones.
	* config/i386/sse.md: Update VFIXUPIMM* patterns.
	(<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
	(<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
	(<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Update.
	(avx512f_sfixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
	(avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
	(avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Update.
	* config/i386/subst.md:
	(round_saeonly_sd_mask_operand4): Add new subst_attr.
	(round_saeonly_sd_mask_op4): Ditto.
	(round_saeonly_expand_operand5): Ditto.
	(round_saeonly_expand): Update.

gcc/testsuite/ChangeLog
2019-01-17  Wei Xiao  <wei3.xiao@intel.com>

	PR target/88794
	Revert:
	2018-11-06  Wei Xiao  <wei3.xiao@intel.com>

	* gcc.target/i386/avx-1.c: Update tests for VFIXUPIMM* intrinsics.
	* gcc.target/i386/avx512f-vfixupimmpd-1.c: Ditto.
	* gcc.target/i386/avx512f-vfixupimmpd-2.c: Ditto.
	* gcc.target/i386/avx512f-vfixupimmps-1.c: Ditto.
	* gcc.target/i386/avx512f-vfixupimmsd-1.c: Ditto.
	* gcc.target/i386/avx512f-vfixupimmsd-2.c: Ditto.
	* gcc.target/i386/avx512f-vfixupimmss-1.c: Ditto.
	* gcc.target/i386/avx512f-vfixupimmss-2.c: Ditto.
	* gcc.target/i386/avx512vl-vfixupimmpd-1.c: Ditto.
	* gcc.target/i386/avx512vl-vfixupimmps-1.c: Ditto.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/testimm-10.c: Ditto.
	* gcc.target/i386/testround-1.c: Ditto.

From-SVN: r268013

2019-01-17  Wei Xiao  <wei3.xiao@intel.com>

        PR target/88794
        Revert:
        2018-11-12  Wei Xiao  <wei3.xiao@intel.com>

        * config/i386/sse.md: Combine VFIXUPIMM* patterns
        (<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
        (<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
        (<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Remove.
        (avx512f_sfixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
        (avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
        (avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Remove.

From-SVN: r268012

gcc/ChangeLog:
2019-01-17  Wei Xiao  <wei3.xiao@intel.com>

        PR target/88794
        Revert:
        2018-12-15  Jakub Jelinek  <jakub@redhat.com>

        PR target/88489
        * config/i386/sse.md (UNSPEC_SFIXUPIMM): New unspec enumerator.
        (avx512f_sfixupimm<mode><mask_name><round_saeonly_name>): Use it
        instead of UNSPEC_FIXUPIMM.

gcc/testsuite/ChangeLog:
2019-01-17  Wei Xiao  <wei3.xiao@intel.com>

        PR target/88794
        Revert:
        2018-12-15  Jakub Jelinek  <jakub@redhat.com>

        PR target/88489
        * gcc.target/i386/avx512vl-vfixupimmsd-2.c: New test.
        * gcc.target/i386/avx512vl-vfixupimmss-2.c: New test.

From-SVN: r268011

2019-01-17  Kewen Lin  <linkw@gcc.gnu.org>

gcc/ChangeLog
    * doc/extend.texi: Add four new prototypes for vec_ld and seven new
    prototypes for vec_st.
    * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add entries
    for scalar address type variants of altivec_vec_ld/altivec_vec_st,
    mainly on signed/unsigned long long and double.

gcc/testsuite/ChangeLog
    * gcc.target/powerpc/altivec_vld_vst_addr.c: New test.

From-SVN: r268007

2019-01-16  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use
	correct max nunits for endian swap.
	(aarch64_expand_fcmla_builtin): Correct subreg code.
	* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
	aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>): Correct
	lane endianness.

From-SVN: r267983

	* config/alpha/alpha.c (alpha_gimplify_va_arg):
	Handle split indirect COMPLEX_TYPE arguments.

From-SVN: r267973

Further investigation showed that my previous patch for this issue was
still incomplete.

The problem stemmed from what I suspect was a mis-understanding of the
way overflow is calculated on aarch64 when values are subtracted (and
hence in comparisons).  In this case, unlike addition, the carry flag
is /cleared/ if there is overflow (technically, underflow) and set
when that does not happen.  This patch clears up this issue by using
CCmode for all subtractive operations (this can fully describe the
normal overflow conditions without anything particularly fancy);
clears up the way we express normal unsigned overflow using CC_Cmode
(the result of a sum is less than one of the operands) and adds a new
mode, CC_ADCmode to handle expressing overflow of an add-with-carry
operation, where the standard idiom is no-longer sufficient to
describe the overflow condition.

	PR target/86891
	* config/aarch64/aarch64-modes.def: Add comment about how the carry
	bit is set by add and compare.
	(CC_ADC): New CC_MODE.
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Use variables
	to cache the code and mode of X.  Adjust the shape of a CC_Cmode
	comparison.  Add detection for CC_ADCmode.
	(aarch64_get_condition_code_1): Update code support for CC_Cmode.  Add
	CC_ADCmode.
	* config/aarch64/aarch64.md (uaddv<mode>4): Use LTU with CCmode.
	(uaddvti4): Comparison result is in CC_ADCmode and the condition is GEU.
	(add<mode>3_compareC_cconly_imm): Delete.  Merge into...
	(add<mode>3_compareC_cconly): ... this.  Restructure the comparison
	to eliminate the need for zero-extending the operands.
	(add<mode>3_compareC_imm): Delete.  Merge into ...
	(add<mode>3_compareC): ... this.  Restructure the comparison to
	eliminate the need for zero-extending the operands.
	(add<mode>3_carryin): Use LTU for the overflow detection.
	(add<mode>3_carryinC): Use CC_ADCmode for the result of the carry out.
	Reexpress comparison for overflow.
	(add<mode>3_carryinC_zero): Update for change to add<mode>3_carryinC.
	(add<mode>3_carryinC): Likewise.
	(add<mode>3_carryinV): Use LTU for carry between partials.
	* config/aarch64/predicates.md (aarch64_carry_operation): Update
	handling of CC_Cmode and add CC_ADCmode.
	(aarch64_borrow_operation): Likewise.

From-SVN: r267971

gcc/ChangeLog:

	* config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): Remove patternmode.
	* config/arm/arm.c (neon_vcmla_lane_prepare_operands): Likewise.
	* config/arm/neon.md (neon_vcmla_lane<rot><mode>, neon_vcmla_laneq<rot><mode>,
	neon_vcmlaq_lane<rot><mode>): Remove endianness conversion.

From-SVN: r267969

2019-01-16  Martin Liska  <mliska@suse.cz>

	* Makefile.in: Set TOOL_INCLUDE_DIR and NATIVE_SYSTEM_HEADER_DIR
	for GCC driver.
	* config/gnu-user.h (TARGET_F951_OPTIONS): Add 'finclude%s/' as
	a new argument.
	* gcc.c (add_sysrooted_hdrs_prefix): New function.
	(path_prefix_reset): Move up in the source file.
	(find_fortran_preinclude_file): Make complex search for the
	fortran header files.

From-SVN: r267967

2019-01-15  Tom de Vries  <tdevries@suse.de>

	PR target/80547
	* config/nvptx/nvptx.c (nvptx_goacc_reduction_init): Handle
	lhs == NULL_TREE for gang-level reduction.

	* testsuite/libgomp.oacc-c-c++-common/gang-reduction-var-assignment.c:
	New test.

From-SVN: r267934

	PR rtl-optimization/88796
	* emit-rtl.h (struct rtl_data): Add stack_protect_guard_decl field.
	* cfgexpand.c (stack_protect_prologue): Initialize
	crtl->stack_protect_guard_decl.
	* function.c (stack_protect_epilogue): Use it instead of calling
	targetm.stack_protect_guard again.
	* dse.c (check_mem_read_rtx): Ignore MEM_VOLATILE_P reads from
	MEMs with MEM_EXPR equal to crtl->stack_protect_guard or
	crtl->stack_protect_guard_decl.
	* config/i386/i386.c (ix86_stack_protect_guard): Set TREE_THIS_VOLATILE
	on the returned MEM_EXPR.

	* gcc.target/i386/pr88796.c: New test.

From-SVN: r267916

From-SVN: r267914

Enable setting vector length using -fopenacc-dim, f.i. -fopenacc-dim=::128.

2019-01-12  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (nvptx_goacc_validate_dims_1): Alow setting
	vector length using -fopenacc-dim.

	* plugin/plugin-nvptx.c (nvptx_exec): Update error message.

From-SVN: r267896

Allow vector_length clauses to accept values larger than warp size.  Note that
this does not enable setting vector_length to values larger than warp size using
-fopenacc-dim.

2019-01-12  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (nvptx_goacc_validate_dims): Take larger vector
	lengths into account.

	* testsuite/libgomp.oacc-c-c++-common/vector-length-128-1.c: Expect
	vector length to be 128.
	* testsuite/libgomp.oacc-c-c++-common/parallel-dims.c: Expect vector
	length 2097152 to be reduced to 1024 instead of 32.

From-SVN: r267889

	* config/i386/gnu.h (TARGET_THREAD_SSP_OFFSET): Define.
	(TARGET_CAN_SPLIT_STACK): Define.
	(TARGET_THREAD_SPLIT_STACK_OFFSET): Define.

From-SVN: r267886

Make "[nvptx] Force vl32 if calling vector-partitionable routines" work as well
if vector length is set by modifying PTX_DEFAULT_VECTOR_LENGTH.

2019-01-12  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (nvptx_goacc_validate_dims_1): In offloading
	region calling vector-partitionable routine, set default_vector_length
	to WARP_SIZE.

From-SVN: r267879

In nvptx_goacc_validate_dims_1, allow oacc_default_dims[DIM_VECTOR] to be
overridden, by assigning it to a new variable default_vector_length at the
start, and using it at the end.

2019-01-12  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (nvptx_goacc_validate_dims_1): Add an use new
	variable default_vector_length.

From-SVN: r267878

There's a problem in oacc_validate_dims that when f.i. the worker dimension
is set using -fopenacc-dim=:32, and the vector_length is set using a
"vector_length (128)" clause, the compiler combines, accepts and emits the
values, while the combination of the two is invalid.

The reason for this is that while oacc_validate_dims validates the dimensions
using targetm.goacc.validate_dims before applying default or minimum values,
it does not do so afterwards.

Work around this in the nvptx port by applying the defaults from
oacc_default_dims at the end of nvptx_goacc_validate_dims_1, as
oacc_validate_dims would do it, and then apply the dimensions limits.

2019-01-12  Tom de Vries  <tdevries@suse.de>

	PR middle-end/88703
	* config/nvptx/nvptx.c (nvptx_goacc_validate_dims_1): Apply defaults
	from oacc_default_dims, as oacc_validate_dims would do it, and apply
	dimensions limits.

From-SVN: r267877

Add a used parameter to TARGET_GOACC_VALIDATE_DIMS, allowing a target to make
decisions in the hook implementation based on whether a dimension is used or
not.

2019-01-12  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (nvptx_goacc_validate_dims_1)
	(nvptx_goacc_validate_dims): Add used parameter.
	* doc/tm.texi: Regenerate.
	* omp-offload.c (oacc_parse_default_dims, oacc_validate_dims): Add
	argument to call to targetm.goacc.validate_dims.
	(default_goacc_validate_dims): Add used
	parameter.
	* target.def (validate_dims): Add used parameter in DEFHOOK.
	* targhooks.h (default_goacc_validate_dims): Add used parameter.

From-SVN: r267876

From-SVN: r267850

2019-01-11  Steve Ellcey  <sellcey@marvell.com>

	* config/aarch64/aarch64.c (aarch64_simd_call_p): New function.
	(aarch64_hard_regno_call_part_clobbered): Add insn argument.
	(aarch64_return_call_with_max_clobbers): New function.
	(TARGET_RETURN_CALL_WITH_MAX_CLOBBERS): New macro.
	* config/avr/avr.c (avr_hard_regno_call_part_clobbered): Add insn
	argument.
	* config/i386/i386.c (ix86_hard_regno_call_part_clobbered): Ditto.
	* config/mips/mips.c (mips_hard_regno_call_part_clobbered): Ditto.
	* config/rs6000/rs6000.c (rs6000_hard_regno_call_part_clobbered): Ditto.
	* config/s390/s390.c (s390_hard_regno_call_part_clobbered): Ditto.
	* cselib.c (cselib_process_insn): Add argument to
	targetm.hard_regno_call_part_clobbered call.
	* ira-conflicts.c (ira_build_conflicts): Ditto.
	* ira-costs.c (ira_tune_allocno_costs): Ditto.
	* lra-constraints.c (inherit_reload_reg): Ditto.
	* lra-int.h (struct lra_reg): Add call_insn field, remove call_p field.
	* lra-lives.c (check_pseudos_live_through_calls): Add call_insn
	argument.  Call targetm.return_call_with_max_clobbers.
	Add argument to targetm.hard_regno_call_part_clobbered call.
	(calls_have_same_clobbers_p): New function.
	(process_bb_lives): Add call_insn and last_call_insn variables.
	Pass call_insn to check_pseudos_live_through_calls.
	Modify if stmt to check targetm.return_call_with_max_clobbers.
	Update setting of flush variable.
	(lra_create_live_ranges_1): Set call_insn to NULL instead of call_p
	to false.
	* lra.c (initialize_lra_reg_info_element): Set call_insn to NULL.
	* regcprop.c (copyprop_hardreg_forward_1): Add argument to
        targetm.hard_regno_call_part_clobbered call.
	* reginfo.c (choose_hard_reg_mode): Ditto.
	* regrename.c (check_new_reg_p): Ditto.
	* reload.c (find_equiv_reg): Ditto.
	* reload1.c (emit_reload_insns): Ditto.
	* sched-deps.c (deps_analyze_insn): Ditto.
	* sel-sched.c (init_regs_for_mode): Ditto.
	(mark_unavailable_hard_regs): Ditto.
	* targhooks.c (default_dwarf_frame_reg_mode): Ditto.
	* target.def (hard_regno_call_part_clobbered): Add insn argument.
	(return_call_with_max_clobbers): New target function.
	* doc/tm.texi: Regenerate.
	* doc/tm.texi.in (TARGET_RETURN_CALL_WITH_MAX_CLOBBERS): New hook.
	* hooks.c (hook_bool_uint_mode_false): Change to
	hook_bool_insn_uint_mode_false.
	* hooks.h (hook_bool_uint_mode_false): Ditto.

From-SVN: r267848

2019-01-11  Steve Ellcey  <sellcey@marvell.com>

	* config/aarch64/aarch64.c (aarch64_simd_call_p): New function.
	(aarch64_remove_extra_call_preserved_regs): New function.
	(TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New macro.
	* doc/tm.texi.in (TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New hook.
	* doc/tm.texi: Regenerate.
	* final.c (get_call_reg_set_usage): Call new hook.
	* target.def (remove_extra_call_preserved_regs): New hook.
	* targhooks.c (default_remove_extra_call_preserved_regs): New function.
	* targhooks.h (default_remove_extra_call_preserved_regs): New function.

From-SVN: r267846

When using a compiler build with:
...
+#define PTX_DEFAULT_VECTOR_LENGTH PTX_CTA_SIZE
...

consider a test-case:
...
int
main (void)
{
  #pragma acc parallel vector_length (64)
    #pragma acc loop worker
    for (unsigned int i = 0; i < 32; i++)
      #pragma acc loop vector
      for (unsigned int j = 0; j < 64; j++)
        ;

  return 0;
}
...

If num_workers is 16, either because:
- we add a "num_workers (16)" clause on the parallel directive, or
- we set "GOMP_OPENACC_DIM=:16:", or
- the libgomp plugin chooses 16 num_workers
we run into an illegal instruction at runtime, because a bar.sync instruction
tries to use a barrier 16.  The instruction is illegal, because ptx supports
only 16 barriers per CTA, and the valid range is 0..15.

The problem is that with a warp-multiple vector length, we use a code generation
scheme with a per-worker barrier.  And because barrier zero is reserved for
per-cta barrier, only the remaining 15 barriers can be used as per-worker
barrier, and consequently we can't use num_workers larger than 15.

This problem occurs only for vector_length 64.  For vector_length 32, we use a
different code generation scheme, and for vector_length >= 96, the maximum
num_workers is not big enough not to trigger this problem.

Also, this problem only occurs for num_workers 16.  As explained above,
num_workers 15 is safe to use, and 16 is already the maximum num_workers for
vector_length 64.

This patch fixes the problem in both the compiler (handling "num_workers (16)")
and in the libgomp nvptx plugin (with and without "GOMP_OPENACC_DIM=:16:").

2019-01-11  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (PTX_CTA_NUM_BARRIERS, PTX_PER_CTA_BARRIER)
	(PTX_NUM_PER_CTA_BARRIER, PTX_FIRST_PER_WORKER_BARRIER)
	(PTX_NUM_PER_WORKER_BARRIERS): Define.
	(nvptx_apply_dim_limits): Prevent vector_length 64 and
	num_workers 16.

	* plugin/plugin-nvptx.c (nvptx_exec): Prevent vector_length 64 and
	num_workers 16.

From-SVN: r267838

Move the defition of PTX_CTA_SIZE up in nvptx.c.

2019-01-11  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.c (PTX_CTA_SIZE): Move up.

From-SVN: r267837

For 64-bit these should not be emitted without suffix in AT&T mode (as
being ambiguous that way); the suffixes are benign for 32-bit. For
consistency also omit the suffix in Intel mode for {,V}CVTSI2SxQ.

The omission has originally (prior to rev 260691) lead to wrong code
being generated for the 64-bit unsigned-to-float/double conversions (as
gas guesses an L suffix instead of the required Q one when the operand
is in memory). In all remaining cases (being changed here) the omission
would "just" lead to warnings with future gas versions.

As a result, arrange to check for the L suffixes in 32-bit test cases.

In order for related test cases to actually test what they're supposed
to test, add (seemingly unrelated) a few empty "asm volatile()".
Presumably there are more where constant propagation voids the intended
effect of the tests, but these are ones helping make sure the assembler
actually still assembles correctly the output after the changes here.

From-SVN: r267833

	PR target/88785
	* config/i386/sse.md (float<floatunssuffix>v2div2sf2): Turn into
	define_expand.
	(*float<floatunssuffix>v2div2sf2): New define_insn.
	(float<floatunssuffix>v2div2sf2_mask): Turn into define_expand.
	(*float<floatunssuffix>v2div2sf2_mask): New define_insn.
	(*float<floatunssuffix>v2div2sf2_mask_1): Replace
	subrtxes (const_vector:V2SF [(const_int 0) (const_int 0)]) with
	match_operands with "const0_operand" "C".

	* g++.target/i386/pr88785.C: New test.

From-SVN: r267825

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_init_builtins): Move aarch64_init_fcmla_laneq_builtins...
	(aarch64_init_simd_builtins): ...Here.

From-SVN: r267824

This allows to use unified asm syntax when compiling for the
ARM instruction. This matches documentation and seems what the
initial patch was intended doing when the flag got added.

2019-01-10  Stefan Agner  <stefan@agner.ch>

	PR target/88648
	* config/arm/arm.c (arm_option_override_internal): Force
	opts->x_inline_asm_unified to true only if TARGET_THUMB2_P.

	* gcc.target/arm/pr88648-asm-syntax-unified.c: Add test to
	check if -masm-syntax-unified gets applied properly.

From-SVN: r267804

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/arm/arm-builtins.c
	(enum arm_type_qualifiers): Add qualifier_lane_pair_index.
	(MAC_LANE_PAIR_QUALIFIERS): New.
	(arm_expand_builtin_args): Use it.
	(arm_expand_builtin_1): Likewise.
	* config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): New.
	* config/arm/arm.c (neon_vcmla_lane_prepare_operands): New.
	* config/arm/arm-c.c (arm_cpu_builtins): Add __ARM_FEATURE_COMPLEX.
	* config/arm/arm_neon.h:
	(vcadd_rot90_f16): New.
	(vcaddq_rot90_f16): New.
	(vcadd_rot270_f16): New.
	(vcaddq_rot270_f16): New.
	(vcmla_f16): New.
	(vcmlaq_f16): New.
	(vcmla_lane_f16): New.
	(vcmla_laneq_f16): New.
	(vcmlaq_lane_f16): New.
	(vcmlaq_laneq_f16): New.
	(vcmla_rot90_f16): New.
	(vcmlaq_rot90_f16): New.
	(vcmla_rot90_lane_f16): New.
	(vcmla_rot90_laneq_f16): New.
	(vcmlaq_rot90_lane_f16): New.
	(vcmlaq_rot90_laneq_f16): New.
	(vcmla_rot180_f16): New.
	(vcmlaq_rot180_f16): New.
	(vcmla_rot180_lane_f16): New.
	(vcmla_rot180_laneq_f16): New.
	(vcmlaq_rot180_lane_f16): New.
	(vcmlaq_rot180_laneq_f16): New.
	(vcmla_rot270_f16): New.
	(vcmlaq_rot270_f16): New.
	(vcmla_rot270_lane_f16): New.
	(vcmla_rot270_laneq_f16): New.
	(vcmlaq_rot270_lane_f16): New.
	(vcmlaq_rot270_laneq_f16): New.
	(vcadd_rot90_f32): New.
	(vcaddq_rot90_f32): New.
	(vcadd_rot270_f32): New.
	(vcaddq_rot270_f32): New.
	(vcmla_f32): New.
	(vcmlaq_f32): New.
	(vcmla_lane_f32): New.
	(vcmla_laneq_f32): New.
	(vcmlaq_lane_f32): New.
	(vcmlaq_laneq_f32): New.
	(vcmla_rot90_f32): New.
	(vcmlaq_rot90_f32): New.
	(vcmla_rot90_lane_f32): New.
	(vcmla_rot90_laneq_f32): New.
	(vcmlaq_rot90_lane_f32): New.
	(vcmlaq_rot90_laneq_f32): New.
	(vcmla_rot180_f32): New.
	(vcmlaq_rot180_f32): New.
	(vcmla_rot180_lane_f32): New.
	(vcmla_rot180_laneq_f32): New.
	(vcmlaq_rot180_lane_f32): New.
	(vcmlaq_rot180_laneq_f32): New.
	(vcmla_rot270_f32): New.
	(vcmlaq_rot270_f32): New.
	(vcmla_rot270_lane_f32): New.
	(vcmla_rot270_laneq_f32): New.
	(vcmlaq_rot270_lane_f32): New.
	(vcmlaq_rot270_laneq_f32): New.
	* config/arm/arm_neon_builtins.def (vcadd90, vcadd270, vcmla0, vcmla90,
	vcmla180, vcmla270, vcmla_lane0, vcmla_lane90, vcmla_lane180, vcmla_lane270,
	vcmla_laneq0, vcmla_laneq90, vcmla_laneq180, vcmla_laneq270,
	vcmlaq_lane0, vcmlaq_lane90, vcmlaq_lane180, vcmlaq_lane270): New.
	* config/arm/neon.md (neon_vcmla_lane<rot><mode>,
	neon_vcmla_laneq<rot><mode>, neon_vcmlaq_lane<rot><mode>): New.
	* config/arm/arm.c (arm_arch8_3, arm_arch8_4): New.
	* config/arm/arm.h (TARGET_COMPLEX, arm_arch8_3, arm_arch8_4): New.
	(arm_option_reconfigure_globals): Use them.
	* config/arm/iterators.md (VDF, VQ_HSF): New.
	(VCADD, VCMLA): New.
	(VF_constraint, rot, rotsplit1, rotsplit2): Add V4HF and V8HF.
	* config/arm/neon.md (neon_vcadd<rot><mode>, neon_vcmla<rot><mode>): New.
	* config/arm/unspecs.md (UNSPEC_VCADD90, UNSPEC_VCADD270,
	UNSPEC_VCMLA, UNSPEC_VCMLA90, UNSPEC_VCMLA180, UNSPEC_VCMLA270): New.

gcc/testsuite/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: Add AArch32 regexpr.
	* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: Likewise.

From-SVN: r267796

gcc/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
	(emit-rtl.h): Include.
	(TYPES_QUADOP_LANE_PAIR): New.
	(aarch64_simd_expand_args): Use it.
	(aarch64_simd_expand_builtin): Likewise.
	(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
	(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
	AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
	aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
	(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
	(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
 	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
	* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
	* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
	fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
	fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
	fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
	* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
	aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
	aarch64_fcmla<rot><mode>): New.
	* config/aarch64/arm_neon.h:
	(vcadd_rot90_f16): New.
	(vcaddq_rot90_f16): New.
	(vcadd_rot270_f16): New.
	(vcaddq_rot270_f16): New.
	(vcmla_f16): New.
	(vcmlaq_f16): New.
	(vcmla_lane_f16): New.
	(vcmla_laneq_f16): New.
	(vcmlaq_lane_f16): New.
	(vcmlaq_rot90_lane_f16): New.
	(vcmla_rot90_laneq_f16): New.
	(vcmla_rot90_lane_f16): New.
	(vcmlaq_rot90_f16): New.
	(vcmla_rot90_f16): New.
	(vcmlaq_laneq_f16): New.
	(vcmla_rot180_laneq_f16): New.
	(vcmla_rot180_lane_f16): New.
	(vcmlaq_rot180_f16): New.
	(vcmla_rot180_f16): New.
	(vcmlaq_rot90_laneq_f16): New.
	(vcmlaq_rot270_laneq_f16): New.
	(vcmlaq_rot270_lane_f16): New.
	(vcmla_rot270_laneq_f16): New.
	(vcmlaq_rot270_f16): New.
	(vcmla_rot270_f16): New.
	(vcmlaq_rot180_laneq_f16): New.
	(vcmlaq_rot180_lane_f16): New.
	(vcmla_rot270_lane_f16): New.
	(vcadd_rot90_f32): New.
	(vcaddq_rot90_f32): New.
	(vcaddq_rot90_f64): New.
	(vcadd_rot270_f32): New.
	(vcaddq_rot270_f32): New.
	(vcaddq_rot270_f64): New.
	(vcmla_f32): New.
	(vcmlaq_f32): New.
	(vcmlaq_f64): New.
	(vcmla_lane_f32): New.
	(vcmla_laneq_f32): New.
	(vcmlaq_lane_f32): New.
	(vcmlaq_laneq_f32): New.
	(vcmla_rot90_f32): New.
	(vcmlaq_rot90_f32): New.
	(vcmlaq_rot90_f64): New.
	(vcmla_rot90_lane_f32): New.
	(vcmla_rot90_laneq_f32): New.
	(vcmlaq_rot90_lane_f32): New.
	(vcmlaq_rot90_laneq_f32): New.
	(vcmla_rot180_f32): New.
	(vcmlaq_rot180_f32): New.
	(vcmlaq_rot180_f64): New.
	(vcmla_rot180_lane_f32): New.
	(vcmla_rot180_laneq_f32): New.
	(vcmlaq_rot180_lane_f32): New.
	(vcmlaq_rot180_laneq_f32): New.
	(vcmla_rot270_f32): New.
	(vcmlaq_rot270_f32): New.
	(vcmlaq_rot270_f64): New.
	(vcmla_rot270_lane_f32): New.
	(vcmla_rot270_laneq_f32): New.
	(vcmlaq_rot270_lane_f32): New.
	(vcmlaq_rot270_laneq_f32): New.
	* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
	* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
	UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
	(FCADD, FCMLA): New.
	(rot): New.
	* config/arm/types.md (neon_fcadd, neon_fcmla): New.

gcc/testsuite/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.

From-SVN: r267795

2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [4/5]

	gcc/
	* config/pa/pa.c: Change "can not" to "cannot".
	* gimple-ssa-evrp-analyze.c: Likewise.
	* ipa-icf.c: Likewise.
	* ipa-polymorphic-call.c: Likewise.
	* ipa-pure-const.c: Likewise.
	* lra-constraints.c: Likewise.
	* lra-remat.c: Likewise.
	* reload1.c: Likewise.
	* reorg.c: Likewise.
	* tree-ssa-uninit.c: Likewise.

	gcc/ada/
	* exp_ch11.adb: Change "can not" to "cannot".
	* sem_ch4.adb: Likewise.

	gcc/fortran/
	* expr.c: Change "can not" to "cannot".

	libobjc/
	* objc/runtime.h: Change "can not" to "cannot".

From-SVN: r267786

2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [1/5]

	contrib/
	* mklog: Mechanically replace "can not" with "cannot".

	gcc/
	* Makefile.in: Mechanically replace "can not" with "cannot".
	* alias.c: Likewise.
	* builtins.c: Likewise.
	* calls.c: Likewise.
	* cgraph.c: Likewise.
	* cgraph.h: Likewise.
	* cgraphclones.c: Likewise.
	* cgraphunit.c: Likewise.
	* combine-stack-adj.c: Likewise.
	* combine.c: Likewise.
	* common/config/i386/i386-common.c: Likewise.
	* config/aarch64/aarch64.c: Likewise.
	* config/alpha/sync.md: Likewise.
	* config/arc/arc.c: Likewise.
	* config/arc/predicates.md: Likewise.
	* config/arm/arm-c.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/arm.h: Likewise.
	* config/arm/arm.md: Likewise.
	* config/arm/cortex-r4f.md: Likewise.
	* config/csky/csky.c: Likewise.
	* config/csky/csky.h: Likewise.
	* config/darwin-f.c: Likewise.
	* config/epiphany/epiphany.md: Likewise.
	* config/i386/i386.c: Likewise.
	* config/i386/sol2.h: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/mcore/mcore.h: Likewise.
	* config/microblaze/microblaze.md: Likewise.
	* config/mips/20kc.md: Likewise.
	* config/mips/sb1.md: Likewise.
	* config/nds32/nds32.c: Likewise.
	* config/nds32/predicates.md: Likewise.
	* config/pa/pa.c: Likewise.
	* config/rs6000/e300c2c3.md: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/s390/s390.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/sh.md: Likewise.
	* config/spu/vmx2spu.h: Likewise.
	* cprop.c: Likewise.
	* dbxout.c: Likewise.
	* df-scan.c: Likewise.
	* doc/cfg.texi: Likewise.
	* doc/extend.texi: Likewise.
	* doc/fragments.texi: Likewise.
	* doc/gty.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/lto.texi: Likewise.
	* doc/md.texi: Likewise.
	* doc/objc.texi: Likewise.
	* doc/rtl.texi: Likewise.
	* doc/tm.texi: Likewise.
	* dse.c: Likewise.
	* emit-rtl.c: Likewise.
	* emit-rtl.h: Likewise.
	* except.c: Likewise.
	* expmed.c: Likewise.
	* expr.c: Likewise.
	* fold-const.c: Likewise.
	* genautomata.c: Likewise.
	* gimple-fold.c: Likewise.
	* hard-reg-set.h: Likewise.
	* ifcvt.c: Likewise.
	* ipa-comdats.c: Likewise.
	* ipa-cp.c: Likewise.
	* ipa-devirt.c: Likewise.
	* ipa-fnsummary.c: Likewise.
	* ipa-icf.c: Likewise.
	* ipa-inline-transform.c: Likewise.
	* ipa-inline.c: Likewise.
	* ipa-polymorphic-call.c: Likewise.
	* ipa-profile.c: Likewise.
	* ipa-prop.c: Likewise.
	* ipa-pure-const.c: Likewise.
	* ipa-reference.c: Likewise.
	* ipa-split.c: Likewise.
	* ipa-visibility.c: Likewise.
	* ipa.c: Likewise.
	* ira-build.c: Likewise.
	* ira-color.c: Likewise.
	* ira-conflicts.c: Likewise.
	* ira-costs.c: Likewise.
	* ira-int.h: Likewise.
	* ira-lives.c: Likewise.
	* ira.c: Likewise.
	* ira.h: Likewise.
	* loop-invariant.c: Likewise.
	* loop-unroll.c: Likewise.
	* lower-subreg.c: Likewise.
	* lra-assigns.c: Likewise.
	* lra-constraints.c: Likewise.
	* lra-eliminations.c: Likewise.
	* lra-lives.c: Likewise.
	* lra-remat.c: Likewise.
	* lra-spills.c: Likewise.
	* lra.c: Likewise.
	* lto-cgraph.c: Likewise.
	* lto-streamer-out.c: Likewise.
	* postreload-gcse.c: Likewise.
	* predict.c: Likewise.
	* profile-count.h: Likewise.
	* profile.c: Likewise.
	* recog.c: Likewise.
	* ree.c: Likewise.
	* reload.c: Likewise.
	* reload1.c: Likewise.
	* reorg.c: Likewise.
	* resource.c: Likewise.
	* rtl.def: Likewise.
	* rtl.h: Likewise.
	* rtlanal.c: Likewise.
	* sched-deps.c: Likewise.
	* sched-ebb.c: Likewise.
	* sched-rgn.c: Likewise.
	* sel-sched-ir.c: Likewise.
	* sel-sched.c: Likewise.
	* shrink-wrap.c: Likewise.
	* simplify-rtx.c: Likewise.
	* symtab.c: Likewise.
	* target.def: Likewise.
	* toplev.c: Likewise.
	* tree-call-cdce.c: Likewise.
	* tree-cfg.c: Likewise.
	* tree-complex.c: Likewise.
	* tree-core.h: Likewise.
	* tree-eh.c: Likewise.
	* tree-inline.c: Likewise.
	* tree-loop-distribution.c: Likewise.
	* tree-nrv.c: Likewise.
	* tree-profile.c: Likewise.
	* tree-sra.c: Likewise.
	* tree-ssa-alias.c: Likewise.
	* tree-ssa-dce.c: Likewise.
	* tree-ssa-dom.c: Likewise.
	* tree-ssa-forwprop.c: Likewise.
	* tree-ssa-loop-im.c: Likewise.
	* tree-ssa-loop-ivcanon.c: Likewise.
	* tree-ssa-loop-ivopts.c: Likewise.
	* tree-ssa-loop-niter.c: Likewise.
	* tree-ssa-phionlycprop.c: Likewise.
	* tree-ssa-phiopt.c: Likewise.
	* tree-ssa-propagate.c: Likewise.
	* tree-ssa-threadedge.c: Likewise.
	* tree-ssa-threadupdate.c: Likewise.
	* tree-ssa-uninit.c: Likewise.
	* tree-ssanames.c: Likewise.
	* tree-streamer-out.c: Likewise.
	* tree.c: Likewise.
	* tree.h: Likewise.
	* vr-values.c: Likewise.

	gcc/ada/
	* exp_ch9.adb: Mechanically replace "can not" with "cannot".
	* libgnat/s-regpat.ads: Likewise.
	* par-ch4.adb: Likewise.
	* set_targ.adb: Likewise.
	* types.ads: Likewise.

	gcc/cp/
	* cp-tree.h: Mechanically replace "can not" with "cannot".
	* parser.c: Likewise.
	* pt.c: Likewise.

	gcc/fortran/
	* class.c: Mechanically replace "can not" with "cannot".
	* decl.c: Likewise.
	* expr.c: Likewise.
	* gfc-internals.texi: Likewise.
	* intrinsic.texi: Likewise.
	* invoke.texi: Likewise.
	* io.c: Likewise.
	* match.c: Likewise.
	* parse.c: Likewise.
	* primary.c: Likewise.
	* resolve.c: Likewise.
	* symbol.c: Likewise.
	* trans-array.c: Likewise.
	* trans-decl.c: Likewise.
	* trans-intrinsic.c: Likewise.
	* trans-stmt.c: Likewise.

	gcc/go/
	* go-backend.c: Mechanically replace "can not" with "cannot".
	* go-gcc.cc: Likewise.

	gcc/lto/
	* lto-partition.c: Mechanically replace "can not" with "cannot".
	* lto-symtab.c: Likewise.
	* lto.c: Likewise.

	gcc/objc/
	* objc-act.c: Mechanically replace "can not" with "cannot".

	libbacktrace/
	* backtrace.h: Mechanically replace "can not" with "cannot".

	libgcc/
	* config/c6x/libunwind.S: Mechanically replace "can not" with
	"cannot".
	* config/tilepro/atomic.h: Likewise.
	* config/vxlib-tls.c: Likewise.
	* generic-morestack-thread.c: Likewise.
	* generic-morestack.c: Likewise.
	* mkmap-symver.awk: Likewise.

	libgfortran/
	* caf/single.c: Mechanically replace "can not" with "cannot".
	* io/unit.c: Likewise.

	libobjc/
	* class.c: Mechanically replace "can not" with "cannot".
	* objc/runtime.h: Likewise.
	* sendmsg.c: Likewise.

	liboffloadmic/
	* include/coi/common/COIResult_common.h: Mechanically replace
	"can not" with "cannot".
	* include/coi/source/COIBuffer_source.h: Likewise.

	libstdc++-v3/
	* include/ext/bitmap_allocator.h: Mechanically replace "can not"
	with "cannot".

From-SVN: r267783

	* config/i386/i386-protos.h (ix86_expand_xorsign): New prototype.
	(ix86_split_xorsign): Ditto.
	* config/i386/i386.c (ix86_expand_xorsign): New function.
	(ix86_split_xorsign): Ditto.
	* config/i386/i386.md (UNSPEC_XORSIGN): New unspec.
	(xorsign<mode>3): New expander.
	(xorsign<mode>3_1): New insn_and_split pattern.
	* config/i386/sse.md (xorsign<mode>3): New expander.

testsuite/ChangeLog:

	* lib/target-supports.exp
	(check_effective_target_xorsign): Add i?86-*-* and x86_64-*-* targets.
	* gcc.target/i386/xorsign.c: New test.

From-SVN: r267779

	* config/sparc/sparc.md (*tablejump_sp32): Merge into...
	(*tablejump_sp64): Likewise.
	(*tablejump<P:mode>): ...this.
	(*call_address_sp32): Merge into...
	(*call_address_sp64): Likewise.
	(*call_address<P:mode>): ...this.
	(*call_symbolic_sp32): Merge into...
	(*call_symbolic_sp64): Likewise.
	(*call_symbolic<P:mode>): ...this.
	(call_value): Remove constraint and add predicate.
	(*call_value_address_sp32): Merge into...
	(*call_value_address_sp64): Likewise.
	(*call_value_address<P:mode>): ...this.
	(*call_value_symbolic_sp32): Merge into...
	(*call_value_symbolic_sp64): Likewise.
	(*call_value_symbolic<P:mode>): ...this.
	(*sibcall_symbolic_sp32): Merge into...
	(*sibcall_symbolic_sp64): Likewise.
	(*sibcall_symbolic<P:mode>): ...this.
	(sibcall_value): Remove constraint and add predicate.
	(*sibcall_value_symbolic_sp32): Merge into...
	(*sibcall_value_symbolic_sp64): Likewise.
	(*sibcall_value_symbolic<P:mode>): ...this.
	(window_save): Minor tweak.
	(*branch_sp32): Merge into...
	(*branch_sp64): Likewise.
	(*branch<P:mode>): ...this.

From-SVN: r267774

	PR target/84010
	* config/sparc/sparc.c (sparc_legitimize_tls_address): Only use Pmode
	consistently in TLS address generation and adjust code to the renaming
	of patterns.  Mark calls to __tls_get_addr as const.
	* config/sparc/sparc.md (tgd_hi22): Turn into...
	(tgd_hi22<P:mode>): ...this and use Pmode throughout.
	(tgd_lo10): Turn into...
	(tgd_lo10<P:mode>): ...this and use Pmode throughout.
	(tgd_add32): Merge into...
	(tgd_add64): Likewise.
	(tgd_add<P:mode>): ...this and use Pmode throughout.
	(tldm_hi22): Turn into...
	(tldm_hi22<P:mode>): ...this and use Pmode throughout.
	(tldm_lo10): Turn into...
	(tldm_lo10<P:mode>): ...this and use Pmode throughout.
	(tldm_add32): Merge into...
	(tldm_add64): Likewise.
	(tldm_add<P:mode>): ...this and use Pmode throughout.
	(tldm_call32): Merge into...
	(tldm_call64): Likewise.
	(tldm_call<P:mode>): ...this and use Pmode throughout.
	(tldo_hix22): Turn into...
	(tldo_hix22<P:mode>): ...this and use Pmode throughout.
	(tldo_lox10): Turn into...
	(tldo_lox10<P:mode>): ...this and use Pmode throughout.
	(tldo_add32): Merge into...
	(tldo_add64): Likewise.
	(tldo_add<P:mode>): ...this and use Pmode throughout.
	(tie_hi22): Turn into...
	(tie_hi22<P:mode>): ...this and use Pmode throughout.
	(tie_lo10): Turn into...
	(tie_lo10<P:mode>): ...this and use Pmode throughout.
	(tie_ld64): Use DImode throughout.
	(tie_add32): Merge into...
	(tie_add64): Likewise.
	(tie_add<P:mode>): ...this and use Pmode throughout.
	(tle_hix22_sp32): Merge into...
	(tle_hix22_sp64): Likewise.
	(tle_hix22<P:mode>): ...this and use Pmode throughout.
	(tle_lox22_sp32): Merge into...
	(tle_lox22_sp64): Likewise.
	(tle_lox22<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub_sp32): Merge into...
	(*tldo_ldub_sp64): Likewise.
	(*tldo_ldub<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub1_sp32): Merge into...
	(*tldo_ldub1_sp64): Likewise.
	(*tldo_ldub1<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub2_sp32): Merge into...
	(*tldo_ldub2_sp64): Likewise.
	(*tldo_ldub2<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldsb1_sp32): Merge into...
	(*tldo_ldsb1_sp64): Likewise.
	(*tldo_ldsb1<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldsb2_sp32): Merge into...
	(*tldo_ldsb2_sp64): Likewise.
	(*tldo_ldsb2<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub3_sp64): Use DImode throughout.
	(*tldo_ldsb3_sp64): Likewise.
	(*tldo_lduh_sp32): Merge into...
	(*tldo_lduh_sp64): Likewise.
	(*tldo_lduh<P:mode>): ...this and use Pmode throughout.
	(*tldo_lduh1_sp32): Merge into...
	(*tldo_lduh1_sp64): Likewise.
	(*tldo_lduh1<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldsh1_sp32): Merge into...
	(*tldo_ldsh1_sp64): Likewise.
	(*tldo_ldsh1<P:mode>): ...this and use Pmode throughout.
	(*tldo_lduh2_sp64): Use DImode throughout.
	(*tldo_ldsh2_sp64): Likewise.
	(*tldo_lduw_sp32): Merge into...
	(*tldo_lduw_sp64): Likewise.
	(*tldo_lduw<P:mode>): ...this and use Pmode throughout.
	(*tldo_lduw1_sp64): Use DImode throughout.
	(*tldo_ldsw1_sp64): Likewise.
	(*tldo_ldx_sp64): Likewise.
	(*tldo_stb_sp32): Merge into...
	(*tldo_stb_sp64): Likewise.
	(*tldo_stb<P:mode>): ...this and use Pmode throughout.
	(*tldo_sth_sp32): Merge into...
	(*tldo_sth_sp64): Likewise.
	(*tldo_sth<P:mode>): ...this and use Pmode throughout.
	(*tldo_stw_sp32): Merge into...
	(*tldo_stw_sp64): Likewise.
	(*tldo_stw<P:mode>): ...this and use Pmode throughout.
	(*tldo_stx_sp64): Use DImode throughout.

From-SVN: r267771