Skip to content

R
riscv-gcc-1
Commit 4f853137 by Jan Beulich Committed by Jan Beulich
Options

x86-64: {,V}CVT{,U}SI2Sx are ambiguous without suffix 

For 64-bit these should not be emitted without suffix in AT&T mode (as
being ambiguous that way); the suffixes are benign for 32-bit. For
consistency also omit the suffix in Intel mode for {,V}CVTSI2SxQ.

The omission has originally (prior to rev 260691) lead to wrong code
being generated for the 64-bit unsigned-to-float/double conversions (as
gas guesses an L suffix instead of the required Q one when the operand
is in memory). In all remaining cases (being changed here) the omission
would "just" lead to warnings with future gas versions.

As a result, arrange to check for the L suffixes in 32-bit test cases.

In order for related test cases to actually test what they're supposed
to test, add (seemingly unrelated) a few empty "asm volatile()".
Presumably there are more where constant propagation voids the intended
effect of the tests, but these are ones helping make sure the assembler
actually still assembles correctly the output after the changes here.

From-SVN: r267833
parent 8ce7e3f8
Showing with 50 additions and 19 deletions
gcc/ChangeLog
2019-01-11 Jan Beulich <jbeulich@suse.com>
* config/i386/i386.md (rex64suffix): Add L suffix for SI.
* config/i386/sse.md (cvtusi2<ssescalarmodesuffix>32<round_name>,
sse2_cvtsi2sd): Add {l}.
(sse2_cvtsi2sdq<round_name>): Make q conditional upon AT&T
syntax.
2019-01-10 Jakub Jelinek <jakub@redhat.com>
PR target/88785
......
gcc/config/i386/i386.md
......@@ -1163,7 +1163,7 @@
[(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")])
;; Instruction suffix for REX 64bit operators.
(define_mode_attr rex64suffix [(SI "") (DI "{q}")])
(define_mode_attr rex64suffix [(SI "{l}") (DI "{q}")])
(define_mode_attr rex64namesuffix [(SI "") (DI "q")])
;; This mode iterator allows :P to be used for patterns that operate on
......
gcc/config/i386/sse.md
......@@ -4781,7 +4781,7 @@
(match_operand:VF_128 1 "register_operand" "v")
(const_int 1)))]
"TARGET_AVX512F && <round_modev4sf_condition>"
"vcvtusi2<ssescalarmodesuffix>\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
"vcvtusi2<ssescalarmodesuffix>{l}\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
......@@ -5040,9 +5040,9 @@
(const_int 1)))]
"TARGET_SSE2"
"@
cvtsi2sd\t{%2, %0|%0, %2}
cvtsi2sd\t{%2, %0|%0, %2}
vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
cvtsi2sd{l}\t{%2, %0|%0, %2}
cvtsi2sd{l}\t{%2, %0|%0, %2}
vcvtsi2sd{l}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,direct,*")
......@@ -5062,9 +5062,9 @@
(const_int 1)))]
"TARGET_SSE2 && TARGET_64BIT"
"@
cvtsi2sdq\t{%2, %0|%0, %2}
cvtsi2sdq\t{%2, %0|%0, %2}
vcvtsi2sdq\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
cvtsi2sd{q}\t{%2, %0|%0, %2}
cvtsi2sd{q}\t{%2, %0|%0, %2}
vcvtsi2sd{q}\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,direct,*")
......
gcc/testsuite/ChangeLog
2019-01-11 Jan Beulich <jbeulich@suse.com>
* gcc.target/i386/avx512f-vcvtsd2si-1.c,
gcc.target/i386/avx512f-vcvtss2si-1.c,
gcc.target/i386/avx512f-vcvttsd2si-1.c,
gcc.target/i386/avx512f-vcvttss2si-1.c: Permit l suffix.
* gcc.target/i386/avx512f-vcvtsi2ss-1.c,
gcc.target/i386/avx512f-vcvtusi2sd-1.c,
gcc.target/i386/avx512f-vcvtusi2ss-1.c: Expect l suffix.
* gcc.target/i386/avx512f-vcvtusi2sd-2.c,
gcc.target/i386/avx512f-vcvtusi2sd64-2.c,
gcc.target/i386/avx512f-vcvtusi2ss-2.c,
gcc.target/i386/avx512f-vcvtusi2ss64-2.c: Add asm volatile().
gcc.target/i386/pr19398.c: Permit l or q suffix.
2019-01-11 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/88296
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
/* { dg-final { scan-assembler-times "vcvtsd2si\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtsd2sil?\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128d x;
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss-1.c
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vcvtsi2ss\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtsi2ssl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
/* { dg-final { scan-assembler-times "vcvtss2si\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtss2sil?\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128 x;
......
gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
/* { dg-final { scan-assembler-times "vcvttsd2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvttsd2si\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvttsd2sil?\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvttsd2sil?\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128d x;
......
gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
/* { dg-final { scan-assembler-times "vcvttss2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvttss2si\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvttss2sil?\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvttss2sil?\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128 x;
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-1.c
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtusi2sdl\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-2.c
......@@ -22,7 +22,9 @@ avx512f_test (void)
s1.x = _mm_set_pd (-24.43, -43.35);
s2 = 0xFEDCA987;
asm volatile ("" : "+m" (s2));
res.x = _mm_cvtu32_sd (s1.x, s2);
asm volatile ("" : "+m" (s2));
compute_vcvtusi2sd (s1.a, s2, res_ref);
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-2.c
......@@ -22,7 +22,9 @@ avx512f_test (void)
s1.x = _mm_set_pd (-24.43, -43.35);
s2 = 0xFEDCBA9876543210;
asm volatile ("" : "+m" (s2));
res.x = _mm_cvtu64_sd (s1.x, s2);
asm volatile ("" : "+m" (s2));
compute_vcvtusi2sd (s1.a, s2, res_ref);
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-1.c
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtusi2ssl\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtusi2ssl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-2.c
......@@ -24,7 +24,9 @@ avx512f_test (void)
s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46);
s2 = 0xFEDCA987;
asm volatile ("" : "+m" (s2));
res.x = _mm_cvtu32_ss (s1.x, s2);
asm volatile ("" : "+m" (s2));
compute_vcvtusi2ss (s1.a, s2, res_ref);
......
gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-2.c
......@@ -24,7 +24,9 @@ avx512f_test (void)
s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46);
s2 = 0xFEDCBA9876543210;
asm volatile ("" : "+m" (s2));
res.x = _mm_cvtu64_ss (s1.x, s2);
asm volatile ("" : "+m" (s2));
compute_vcvtusi2ss (s1.a, s2, res_ref);
......
gcc/testsuite/gcc.target/i386/pr19398.c
......@@ -6,4 +6,4 @@ int test (float a)
return (a * a);
}
/* { dg-final { scan-assembler-not "cvttss2si\[^\\n\]*%xmm" } } */
/* { dg-final { scan-assembler-not "cvttss2si\[lq\]?\[^\\n\]*%xmm" } } */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment