* cgraph.h, dbxout.c, dwarfout2.c, gimple-fold.c,
    	lto-streamer-out.c, print-tree.c, symtab.c, tree-inline.c,
    	tree-streamer-in.c, tree-streamer-out.c, tree.c, tree.h,
    	varpool.c: Rename all instances of DECL_ABSTRACT to
    	DECL_ABSTRACT_P.

    cp/
    	* class.c, decl.c, optimize.c: Rename all instances of
    	DECL_ABSTRACT to DECL_ABSTRACT_P.

    lto/
    	* lto-symtab.c, lto.c: Rename all instances of DECL_ABSTRACT to
    	DECL_ABSTRACT_P.

From-SVN: r215567

rs6000.c (insn_is_swappable_p): Don't provide special handling for stores whose SET_SRC is an UNSPEC (such as...

[gcc]

2014-09-24  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (insn_is_swappable_p): Don't provide
	special handling for stores whose SET_SRC is an UNSPEC (such as
	UNSPEC_STVE).


[gcc/testsuite]

2014-09-24  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/swaps-p8-17.c: New test.

From-SVN: r215564

  gcc/
    * shrink-wrap.c (move_insn_for_shrink_wrap): Add further check when
    !REG_P (src) to release more instruction sink opportunities.

  gcc/testsuite/
    * gcc.target/aarch64/shrink_wrap_symbol_ref_1.c: New testcase.

From-SVN: r215563

  2014-09-24  Wilco Dijkstra <wdijkstr@arm.com>

  gcc/
    * config/aarch64/aarch64.c (aarch64_register_move_cost): Add register move
    costs for 128-bit types.

From-SVN: r215562

ipa-prop.c (ipa_edge_duplication_hook): Update controlled_use_count when duplicating a PASS_THROUGH jump function when...

2014-09-24  Martin Jambor  <mjambor@suse.cz>

	* ipa-prop.c (ipa_edge_duplication_hook): Update controlled_use_count
	when duplicating a PASS_THROUGH jump function when creating a
	speculative edge.

From-SVN: r215560

	PR c/61405
	PR c/53874
gcc/
	* asan.c (maybe_instrument_call): Add default case.
	* ipa-pure-const.c (special_builtin_state): Likewise.
	* predict.c (expr_expected_value_1): Likewise.
	* lto-streamer-out.c (write_symbol): Initialize variable.
gcc/c-family/
	* c-common.h (struct c_common_resword): Don't define CPP_KEYWORD.
gcc/c/
	* c-parser.c: Don't define CPP_KEYWORD.
	(c_parser_switch_statement): Pass original type to c_finish_case.
	* c-tree.h (c_finish_case): Update declaration.
	* c-typeck.c (c_finish_case): Add TYPE parameter.  Pass it
	conditionally to c_do_switch_warnings.
gcc/cp/
	* semantics.c (finish_switch_cond): Call unlowered_expr_type.
	* tree.c (bot_manip): Add default case.
	* parser.c (cp_parser_primary_expression): Cast the controlling
	expression of a switch to an int.
	(cp_parser_unqualified_id): Likewise.
gcc/testsuite/
	* c-c++-common/pr53874.c: New test.
	* c-c++-common/pr61405.c: New test.
libcpp/
	* include/cpplib.h (enum cpp_ttype): Define CPP_KEYWORD.

From-SVN: r215559

	* config/aarch64/arm_neon.h (vmuld_lane_f64): Use macro for getting
	the lane.
	(vmuld_laneq_f64): Likewise.
	(vmuls_lane_f32): Likewise.
	(vmuls_laneq_f32): Likewise.

	* gcc.target/aarch64/simd/vmul_lane_const_lane_1.c: New test.

From-SVN: r215553

PR bootstrap/63235

gcc/
	* varpool.c (varpool_node::add): Pass decl attributes
	to lookup_attribute.

From-SVN: r215552

	PR libstdc++/63353
	* src/c++11/ios.cc (ios_base::_M_swap): Fix typo.

From-SVN: r215549

	PR sanitizer/63316
	* asan.c (asan_expand_check_ifn): Fix up align >= 8 optimization.

	* c-c++-common/asan/pr63316.c: New test.

From-SVN: r215547

2014-09-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR tree-optimization/63266
    * tree-ssa-math-opts.c (struct symbolic_number): Add comment about
    marker for unknown byte value.
    (MARKER_MASK): New macro.
    (MARKER_BYTE_UNKNOWN): New macro.
    (HEAD_MARKER): New macro.
    (do_shift_rotate): Mark bytes with unknown values due to sign
    extension when doing an arithmetic right shift. Replace hardcoded
    mask for marker by new MARKER_MASK macro.
    (find_bswap_or_nop_1): Likewise and adjust ORing of two symbolic
    numbers accordingly.

    gcc/testsuite/
    PR tree-optimization/63266
    * gcc.dg/optimize-bswapsi-1.c (swap32_d): New bswap pass test.

From-SVN: r215546

gcc/
	* config/i386/sse.md
	(define_insn
	"<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>"):
	Add masking.
	(define_insn "fix_truncv8sfv8si2<mask_name>"): Ditto.
	(define_insn "fix_truncv4sfv4si2<mask_name>"): Ditto.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215545

gcc/
	* config/i386/sse.md
	(define_c_enum "unspec"): Add UNSPEC_PSHUFHW, UNSPEC_PSHUFLW.
	(define_insn "<mask_codefor>avx512bw_pshuflwv32hi<mask_name>"): New.
	(define_expand "avx512vl_pshuflwv3_mask"): Ditto.
	(define_insn "avx2_pshuflw_1<mask_name>"): Add masking.
	(define_expand "avx512vl_pshuflw_mask"): New.
	(define_insn "sse2_pshuflw_1<mask_name>"): Add masking.
	(define_insn "<mask_codefor>avx512bw_pshufhwv32hi<mask_name>"): New.
	(define_expand "avx512vl_pshufhwv3_mask"): Ditto.
	(define_insn "avx2_pshufhw_1<mask_name>"): Add masking.
	(define_expand "avx512vl_pshufhw_mask"): New.
	(define_insn "sse2_pshufhw_1<mask_name>"): Add masking.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215544

gcc/
	* config/i386/i386.c
	(ix86_expand_args_builtin): Handle CODE_FOR_sse2_shufpd,
	CODE_FOR_sse2_sse2_shufpd_mask, CODE_FOR_sse2_avx512dq_shuf_f64x2_mask,
	CODE_FOR_sse2_avx512dq_shuf_i64x2_mask,
	CODE_FOR_sse2_avx512vl_shuf_i32x4_mask and
	CODE_FOR_sse2_avx512vl_shuf_f32x4_mask.
	* config/i386/sse.md
	(define_expand "avx512dq_shuf_<shuffletype>64x2_mask"): New.
	(define_insn
	"<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>"): Ditto.
	(define_expand "avx512vl_shuf_<shuffletype>32x4_mask"): Ditto.
	(define_insn
	"<mask_codefor>avx512vl_shuf_<shuffletype>32x4_1<mask_name>"): Ditto.
	(define_expand "avx512vl_pshufdv3_mask"): Ditto.
	(define_insn "avx2_pshufd_1<mask_name>"): Add masking.
	(define_expand "avx512vl_pshufd_mask"): New.
	(define_insn "sse2_pshufd_1<mask_name>"): Add masking.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215543

gcc/
	* config/i386/i386.c
	(CODE_FOR_avx2_extracti128): Rename to ...
	(CODE_FOR_avx_vextractf128v4di): this.
	(CODE_FOR_avx2_inserti128): Rename to ...
	(CODE_FOR_avx_vinsertf128v4di): this.
	(ix86_expand_args_builtin): Handle CODE_FOR_avx_vinsertf128v4di,
	CODE_FOR_avx_vextractf128v4di.
	(ix86_expand_args_builtin): Handle CODE_FOR_avx512dq_vinsertf32x8_mask,
	CODE_FOR_avx512dq_vinserti32x8_mask, CODE_FOR_avx512vl_vinsertv4df,
	CODE_FOR_avx512vl_vinsertv4di, CODE_FOR_avx512vl_vinsertv8sf,
	CODE_FOR_avx512vl_vinsertv8si.
	* config/i386/sse.md
	(define_expand
	"<extract_type>_vinsert<shuffletype><extract_suf>_mask"): Use
	AVX512_VEC mode iterator.
	(define_insn
	"<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>_1<mask_name>"):
	Ditto.
	(define_expand
	"<extract_type_2>_vinsert<shuffletype><extract_suf_2>_mask"): Use
	AVX512_VEC_2 mode iterator.
	(define_insn "vec_set_lo_<mode><mask_name>"): New.
	(define_insn "vec_set_hi_<mode><mask_name>"): Ditto.
	(define_expand "avx512vl_vinsert<mode>"): Ditto.
	(define_insn "avx2_vec_set_lo_v4di"): Delete.
	(define_insn "avx2_vec_set_hi_v4di"): Ditto.
	(define_insn "vec_set_lo_<mode><mask_name>"): Add masking.
	(define_insn "vec_set_hi_<mode><mask_name>"): Ditto.
	(define_insn "vec_set_lo_<mode><mask_name>"): Ditto.
	(define_insn "vec_set_hi_<mode><mask_name>"): Ditto.
	(define_expand "avx2_extracti128"): Delete.
	(define_expand "avx2_inserti128"): Ditto.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215542

gcc/
	* config/i386/sse.md
	(define_insn "avx2_<code>v16qiv16hi2<mask_name>"): Add masking.
	(define_insn "avx512bw_<code>v32qiv32hi2<mask_name>"): New.
	(define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"): Add masking.
	(define_insn "avx2_<code>v8qiv8si2<mask_name>"): Ditto.
	(define_insn "sse4_1_<code>v4qiv4si2<mask_name>"): Ditto.
	(define_insn "avx2_<code>v8hiv8si2<mask_name>"): Ditto.
	(define_insn "sse4_1_<code>v4hiv4si2<mask_name>"): Ditto.
	(define_insn "avx2_<code>v4qiv4di2<mask_name>"): Ditto.
	(define_insn "sse4_1_<code>v2qiv2di2<mask_name>"): Ditto.
	(define_insn "avx2_<code>v4hiv4di2<mask_name>"): Ditto.
	(define_insn "sse4_1_<code>v2hiv2di2<mask_name>"): Ditto.
	(define_insn "avx2_<code>v4siv4di2<mask_name>"): Ditto.
	(define_insn "sse4_1_<code>v2siv2di2<mask_name>"): Ditto.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215541

re PR rtl-optimization/63210 (ira does not select the best register compared with gcc 4.8 for ARM THUMB1)

ChangeLog:
2014-09-24  Zhenqiang Chen  <zhenqiang.chen@arm.com>

	PR rtl-optimization/63210
	* ira-color.c (assign_hard_reg): Ignore conflict cost if the
	HARD_REGNO is not availabe for CONFLICT_A.

testsuite/ChangeLog:
2014-09-24  Zhenqiang Chen  <zhenqiang.chen@arm.com>

	* gcc.target/arm/pr63210.c: New test.

From-SVN: r215540

Add some simple test cases for noreorder behaving like
-fno-toplevel-reorder and -fno-toplevel-reorder still working.

gcc/testsuite/:

2014-09-23  Andi Kleen  <ak@linux.intel.com>

	* gcc.dg/noreorder.c: New test.
	* gcc.dg/noreorder2.c: New test.
	* gcc.dg/noreorder3.c: New test.
	* gcc.dg/noreorder4.c: New test.

From-SVN: r215538

Some projects need to prevent reordering of specific top level
declarations with LTO, in particular declarations defining init calls.

The only way to do that with LTO was to use -fno-toplevel-reorder,
which stops reordering for all declarations and makes LTO partitioning
less efficient.

This patch adds a new no_reorder attribute that stops reordering only
for the marked declaration. The program can then only mark e.g. the
initcalls and leave all the other declarations alone.

The patch does:

- Adds the new no_reorder attribute for the C family.
- Initializes a new no_reorder flag in the symtab_nodes in the
function visibility flag.
- Maintains the no_reorder flag when creating new nodes.
- Changes the partition code to always keep a separate
sorted queue of ordered nodes and flush them in order with the other
nodes. This is used by all nodes with -fno-toplevel-reorder,
and only the marked ones without it.
Parts of the old -fno-toplevel-reorder code paths are reused.
- Adds various checks throughout the tree to make no_reorder
marked functions behave the same as with -fno-toplevel-reorder
- Changes the LTO streamer to serialize the no_reorder attribute.

gcc/c-family/:

2014-09-23  Andi Kleen  <ak@linux.intel.com>

	* c-common.c (handle_no_reorder_attribute): New function.
	(c_common_attribute_table): Add no_reorder attribute.

gcc/:

2014-09-23  Andi Kleen  <ak@linux.intel.com>

	* cgraph.h (symtab_node): Add no_reorder attribute.
	(symbol_table::output_asm_statements): Remove.
	* cgraphclones.c (cgraph_node::create_clone): Copy no_reorder.
	(cgraph_node::create_version_clone): Dito.
	(symbol_table::output_asm_statements): Remove.
	* trans-mem.c (ipa_tm_create_version_alias): Dito.
	* cgraphunit.c (varpool_node::finalize_decl): Check no_reorder.
	(output_in_order): Add no_reorder flag. Only handle no_reorder
	nodes when set.
	(symbol_table::compile): Add separate pass for no_reorder nodes.
	(process_common_attributes): Set no_reorder flag in symtab node.
	Add node argument.
	(process_function_and_variable_attributes): Pass symtab nodes to
	process_common_attributes.
	* doc/extend.texi (no_reorder): Document no_reorder attribute.
	* lto-cgraph.c (lto_output_node): Serialize no_reorder.
	(lto_output_varpool_node): Dito.
	(input_overwrite_node): Dito.
	(input_varpool_node): Dito.
	* varpool.c (varpool_node::add): Set no_reorder attribute.
	(symbol_table::remove_unreferenced_decls): Handle no_reorder.
	(symbol_table::output_variables): Dito.
	* symtab.c (symtab_node::dump_base): Print no_reorder.

gcc/lto/:

2014-09-23  Andi Kleen  <ak@linux.intel.com>

	* lto-partition.c (node_cmp): Update comment.
	(varpool_node_cmp): Use symtab_node for comparison.
	(add_sorted_nodes): New function.
	(lto_balanced_map): Change to keep ordered queue
	of ordered node. Handle no_reorder attribute.

From-SVN: r215537

From-SVN: r215536

2014-09-23  Jiong Wang  <jiong.wang@arm.com>

gcc/
  * shrink-wrap.c (try_shrink_wrapping): Check PIC_OFFSET_TABLE_REGNUM not
    be INVALID_REGNUM.

From-SVN: r215533

	gcc/
	* configure: Regenerate.

From-SVN: r215532

gcc/:
	* combine.c (simplify_shift_const_1): Allow commuting (ashiftrt (xor))
	when result_mode == shift_mode.

gcc/testsuite/:
	* gcc.dg/combine_ashiftrt_1.c: New test.
	* gcc.dg/combine_ashiftrt_2.c: Likewise.
	* gcc.target/aarch64/singleton_intrinsics_1.c: Remove scan-assembler
	workarounds for cmge.
	* gcc.target/aarch64/simd/int_comparisons_1.c: Likewise; also check for
	absence of mvn.

From-SVN: r215531

include/:
	* demangle.h (DMGL_DLANG): New macro.
	(DMGL_STYLE_MASK): Add DMGL_DLANG.
	(demangling_styles): Add dlang_demangling.
	(DLANG_DEMANGLING_STYLE_STRING): New macro.
	(DLANG_DEMANGLING): New macro.
	(dlang_demangle): New prototype.
libiberty/:
	* Makefile.in (CFILES): Add d-demangle.c.
	(REQUIRED_OFILES): Add d-demangle.o.
	* cplus-dem.c (libiberty_demanglers): Add dlang_demangling case.
	(cplus_demangle): Likewise.
	* d-demangle.c: New file.
	* testsuite/Makefile.in (really-check): Add check-d-demangle.
	* testsuite/d-demangle-expected: New file.

From-SVN: r215530

/cp
2014-09-23  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61857
	* parser.c (cp_parser_skip_to_closing_square_bracket,
	cp_parser_array_designator_p): New.
	(cp_parser_initializer_list): Use the latter.

/testsuite
2014-09-23  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61857
	* g++.dg/cpp1y/lambda-init10.C: New.

From-SVN: r215528

From-SVN: r215527

rs6000.md (f32_vsx): New mode attributes to refine the constraints used on 32/64-bit floating point...

2014-09-23  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (f32_vsx): New mode attributes to
	refine the constraints used on 32/64-bit floating point moves.
	(f32_av): Likewise.
	(f64_vsx): Likewise.
	(f64_dm): Likewise.
	(f64_av): Likewise.
	(BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa.
	(BOOL_REGS_OP1): Likewise.
	(BOOL_REGS_OP2): Likewise.
	(BOOL_REGS_UNARY): Likewise.
	(mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for
	32/64-bit floating point moves.  Do not use wa, instead use ww/ws
	for moves involving VSX registers.  Do not use constraints that
	target VSX registers for decimal types.
	(mov<mode>_hardfloat32, DFmode/DDmode): Likewise.
	(mov<mode>_hardfloat64, DFmode/DDmode): Likewise.

From-SVN: r215521

	* tree.h (int_bit_position): Turn into inline function;
	implement using wide int.
	* tree.c (int_bit_position): Remove.

From-SVN: r215518

	PR fortran/63331
	* trans-types.c (gfc_get_array_descr_info): Build DEBUG_EXPR_DECL
	instead of VAR_DECL for base_decl.

	* gfortran.dg/pr63331.f90: New test.

From-SVN: r215516

gcc/
	PR bootstrap/63280
	* target-globals.c (target_globals::~target_globals): Fix location
	of ira_int destruction.

From-SVN: r215515

	* config/abi/pre/gnu.ver: Adjust basic_ostream exports.
	* include/std/istream (basic_iostream(basic_iostream&&)): Pass *this
	to ostream constructor.
	* include/std/ostream (basic_ostream(basic_iostream*)): Change to take
	parameter by reference, to avoid ambiguity.
	* testsuite/27_io/basic_ostream/cons/char/null.cc: New.

From-SVN: r215510

From-SVN: r215508

From-SVN: r215503

Some subtests were reported as UNSUPPORTED when running under LTO.
That was just because the relevant variables were optimized out.
Mark those variables as used. Now const-volatile reports 192 PASS.

gcc/testsuite/ChangeLog

	* gcc.dg/guality/const-volatile.c (i): Mark as used.
	(ci): Likewise.
	(pci): Likewise.
	(pvi): Likewise.
	(pcvi): Likewise.
	(cip): Likewise.
	(foo): Likewise.
	(cfoo): Likewise.

From-SVN: r215502

Old GDB might show short and long as short int and long int. This made
gcc.dg/guality/const-volatile.c ans restrict.c fail on older GDBs.
According to the patch that changed this in newer versions of GDB
this was a bug: https://sourceware.org/ml/gdb-patches/2012-09/msg00455.html

The patch transforms the types "short int" and "long int" coming from
GDB to plain "short" and "long". And a variant has been added to the
const-volatile.c testcase to make sure short and long long are handled
correctly now with older GDB.

gcc/testsuite/ChangeLog

	* lib/gcc-gdb-test.exp (gdb-test): Transform gdb types "short int"
	and "long int" to plain "short" and "long".
	* gcc.dg/guality/const-volatile.c (struct bar): New struct
	containing short and long long fields.
	(bar): New variable to test the type.

From-SVN: r215501

gcc/
	* cfgcleanup.c (try_optimize_cfg): Do not remove label
	with LABEL_PRESERVE_P flag set.

From-SVN: r215498

2014-09-23  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/62155
	* g++.dg/cpp0x/lambda/lambda-62155.C: New.

From-SVN: r215497

gcc/
	* config/i386/sse.md
	(define_expand "avx_shufpd256<mask_expand4_name>"): Add masking.
	(define_insn "avx_shufpd256_1<mask_name>"): Ditto.
	(define_expand "sse2_shufpd<mask_expand4_name>"): Ditto.
	(define_insn "sse2_shufpd_v2df_mask"): New.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215496

gcc/
	* config/i386/sse.md
	(define_expand "avx_shufps256<mask_expand4_name>"): Add masking.
	(define_insn "avx_shufps256_1<mask_name>"): Ditto.
	(define_expand "sse_shufps<mask_expand4_name>"): Ditto.
	(define_insn "sse_shufps_v4sf_mask"): New.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215495

gcc/
	* config/i386/sse.md
	(define_insn "avx_unpckhps256<mask_name>"): Add masking.
	(define_insn "vec_interleave_highv4sf<mask_name>"): Ditto.
	(define_insn "avx_unpcklps256<mask_name>"): Ditto.
	(define_insn "unpcklps128_mask"): New.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215494