Commit 415ebad0 by Alexander Ivchenko Committed by Kirill Yukhin

AVX-512. Add cvtps2 insn patterns.

gcc/
	* config/i386/sse.md
	(define_insn
	"<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>"):
	Add masking.
	(define_insn "fix_truncv8sfv8si2<mask_name>"): Ditto.
	(define_insn "fix_truncv4sfv4si2<mask_name>"): Ditto.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215545
parent 41755b52
...@@ -8,6 +8,22 @@ ...@@ -8,6 +8,22 @@
Michael Zolotukhin <michael.v.zolotukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md * config/i386/sse.md
(define_insn
"<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>"):
Add masking.
(define_insn "fix_truncv8sfv8si2<mask_name>"): Ditto.
(define_insn "fix_truncv4sfv4si2<mask_name>"): Ditto.
2014-09-24 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md
(define_c_enum "unspec"): Add UNSPEC_PSHUFHW, UNSPEC_PSHUFLW. (define_c_enum "unspec"): Add UNSPEC_PSHUFHW, UNSPEC_PSHUFLW.
(define_insn "<mask_codefor>avx512bw_pshuflwv32hi<mask_name>"): New. (define_insn "<mask_codefor>avx512bw_pshuflwv32hi<mask_name>"): New.
(define_expand "avx512vl_pshuflwv3_mask"): Ditto. (define_expand "avx512vl_pshuflwv3_mask"): Ditto.
...@@ -3937,13 +3937,13 @@ ...@@ -3937,13 +3937,13 @@
(define_mode_attr sf2simodelower (define_mode_attr sf2simodelower
[(V16SI "v16sf") (V8SI "v8sf") (V4SI "v4sf")]) [(V16SI "v16sf") (V8SI "v8sf") (V4SI "v4sf")])
(define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode>" (define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>"
[(set (match_operand:VI4_AVX 0 "register_operand" "=v") [(set (match_operand:VI4_AVX 0 "register_operand" "=v")
(unspec:VI4_AVX (unspec:VI4_AVX
[(match_operand:<ssePSmode> 1 "nonimmediate_operand" "vm")] [(match_operand:<ssePSmode> 1 "nonimmediate_operand" "vm")]
UNSPEC_FIX_NOTRUNC))] UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2" "TARGET_SSE2 && <mask_mode512bit_condition>"
"%vcvtps2dq\t{%1, %0|%0, %1}" "%vcvtps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set (attr "prefix_data16") (set (attr "prefix_data16")
(if_then_else (if_then_else
...@@ -4031,20 +4031,20 @@ ...@@ -4031,20 +4031,20 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "XI")]) (set_attr "mode" "XI")])
(define_insn "fix_truncv8sfv8si2" (define_insn "fix_truncv8sfv8si2<mask_name>"
[(set (match_operand:V8SI 0 "register_operand" "=x") [(set (match_operand:V8SI 0 "register_operand" "=v")
(fix:V8SI (match_operand:V8SF 1 "nonimmediate_operand" "xm")))] (fix:V8SI (match_operand:V8SF 1 "nonimmediate_operand" "vm")))]
"TARGET_AVX" "TARGET_AVX && <mask_avx512vl_condition>"
"vcvttps2dq\t{%1, %0|%0, %1}" "vcvttps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "vex") (set_attr "prefix" "<mask_prefix>")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "fix_truncv4sfv4si2" (define_insn "fix_truncv4sfv4si2<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=v")
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))] (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "vm")))]
"TARGET_SSE2" "TARGET_SSE2 && <mask_avx512vl_condition>"
"%vcvttps2dq\t{%1, %0|%0, %1}" "%vcvttps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set (attr "prefix_rep") (set (attr "prefix_rep")
(if_then_else (if_then_else
...@@ -4057,7 +4057,7 @@ ...@@ -4057,7 +4057,7 @@
(const_string "*") (const_string "*")
(const_string "0"))) (const_string "0")))
(set_attr "prefix_data16" "0") (set_attr "prefix_data16" "0")
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "<mask_prefix2>")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_expand "fixuns_trunc<mode><sseintvecmodelower>2" (define_expand "fixuns_trunc<mode><sseintvecmodelower>2"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment