Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
M
macroplacement
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
macroplacement
Commits
6b4fe784
Commit
6b4fe784
authored
Jul 06, 2022
by
sakundu
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Updated MemPool tile sdc
Signed-off-by: sakundu <sakundu@ucsd.edu>
parent
1ff0c6d0
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
5 additions
and
5 deletions
+5
-5
.gitignore
+2
-2
Flows/ASAP7/mempool_tile/constraints/mempool_tile_wrap.sdc
+1
-1
Flows/NanGate45/mempool_tile/constraints/mempool_tile_wrap.sdc
+1
-1
Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc
+1
-1
No files found.
.gitignore
View file @
6b4fe784
Flows/*/*/run/*/
\ No newline at end of file
Flows/*/*/run/*/
Flows/job
Flows/ASAP7/mempool_tile/constraints/mempool_tile_wrap.sdc
View file @
6b4fe784
...
...
@@ -1299,4 +1299,4 @@ set_clock_uncertainty -setup 0.08 [get_clocks clk_i]
set_clock_uncertainty -hold 0.08 [get_clocks clk_i]
set_clock_latency 0.07 [get_clocks vclk_i]
## List of unsupported SDC commands ##
set_critical_range 0.100 [current_design]
#
set_critical_range 0.100 [current_design]
Flows/NanGate45/mempool_tile/constraints/mempool_tile_wrap.sdc
View file @
6b4fe784
...
...
@@ -56,4 +56,4 @@ set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
set_critical_range 0.100 [current_design]
#
set_critical_range 0.100 [current_design]
Flows/SKY130HD/mempool_tile/constraints/mempool_tile_wrap.sdc
View file @
6b4fe784
...
...
@@ -56,4 +56,4 @@ set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
set_critical_range 0.100 [current_design]
#
set_critical_range 0.100 [current_design]
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment