| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| main/scala/accel | ||
| test/scala/dut |
[VTA][TSIM] Use Module instead of RawModule for testbench by creating an empty bundle for the IO (#3242) * use Module instead of RawModule for testbench by creating an empty bundle for the IO * change default back to verilog
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| main/scala/accel | Loading commit data... | |
| test/scala/dut | Loading commit data... |