Files · 9e660dbe745bcf24c861dcfa4a4671d333fb5c21 · wenyuanbo / tic · GitLab

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[VERILOG] Basic Verilog Testflow (#70) · 9e660dbe
```
* [VERILOG] Basic Verilog Testflow

* fix build

* fix the comment

* fix lint in verilog
```
Tianqi Chen committed Mar 13, 2017
9e660dbe

Name	Last commit	Last update
HalideIR @ 7efe0366
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dmlc-core @ c2871f5d
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include/tvm		Loading commit data...
make		Loading commit data...
python/tvm		Loading commit data...
src		Loading commit data...
tests		Loading commit data...
verilog		Loading commit data...
.gitignore		Loading commit data...
.gitmodules		Loading commit data...
.travis.yml		Loading commit data...
CMakeLists.txt		Loading commit data...
LICENSE		Loading commit data...
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