* [VERILOG] Basic Verilog Testflow

* fix build

* fix the comment

* fix lint in verilog

* [OP/LANG] Support Extern Call, more regression tests

* [TEST] Include pylintrc

* [IterVar/REFACTOR] Add types to IterVar

* [ARITH/REFACTOR] Move IntSet to include

* [REFACTOR/OP] Move Op detail to seperate folder.

* fix test

* loop_partition draft

* divide loop variable into constant domain and variable domain & consider multiple partitions

* process doubt interval

* fix and refactor, add relax_map arg in BoundDeduce

* fix testcase and comment

* rebase to zero, convert to SSA

* change the logic of generating loop code & fix issues

* add a testcase for relax map in deducebound && fix issues

* clean code

* const auto&

* add test_multi_if

* [ARITH/VISITOR] Modular Analysis, ExprFunctor, StmtFunctor

* retrigger

* [IRFunctor] Migrated CodegenC

* [IRFUNCTOR] Migrate CodeGenLLVM

* [IRFunctor] Migrate canonical

* [IRFunctor] Migrate vectorize

* [IRFunctor] migrate CodeGenStackVM

* [LLVM] Initial support for codegen LLVM.

* Fix the naming issue of codegen

* [FIX] add CombineInterval<Div>

* fix error message and add comment about rounding

* fix comment

* [PYTHON/API] Add compare and logic build-in op for Expr

* remove 'and', 'or'

* add deducer

* [WIP] bound_deducer.cc

* move IntervalSet and StrideSet into int_set_internal.h

* add multiple failure for VariablePathFinder, add EvalSign

* consider round in deduce, add success flag

* remove Visit_(Div)

* add comment, update HalideIR

* expose intset to python

* check the sign of every expr

* set return type as ExprSignType

* fine tune

* add min & max python api for interval set

* support for conditional expr

* refactor test

* add checker for BoundDeducer

* add python check test

* fix

* fix

* change range to interval; remove converter

* remove converter declaration

* remove int_set_internal.h

* [PASS] Change IRVisitor interfaces to function override

* [PASS] Change IRMutator interfaces to overloadable function

* [PYTHON/API] Add compare and logic build-in op for Expr

* remove 'and', 'or'

* [FUSION] add Fusion(Schedule)

* [FUSION] rename to AutoFuseEwise, detect whether the stage has been scheduled

* [FUSION] change to visitor pattern

* [FUSION] rename filename

* [FUSION] fine-tune the interface

* [FUSION] typo

* move elem_wise to schedule

* rename test function

[TEST/PYTHON] Add unittest folder, add a build pipeline. Rename Buffer.ptr to Buffer.data to be consistent with Array. (#29)

* [CODEGEN] CUDA/OPENCL pipeline complete

* Hide TVMType by str in frontend

* [CODEGEN] Add LoweredFunc, MakeAPI and SplitHostDevice

* update halideir