This PR moves the codegen related code into the target folder,
as they are target specific functionalities.

We also adopt the term "compiler driver" in common compiler infra
such as rust, GHC and clang.
As a result, build_module is moved into the driver folder.

TIR is the new namespace for low-level IR
for tensor-level optimizations and loop transformations.

This PR establishes the namespace and files.

- lowered_func.h,buffer.h,data_layout.h -> tir/buffer.h,tir/data_layout.h,tir/lowered_func.h
- ir.h -> tir/expr.h, tir/stmt.h
- ir_functor_ext.h -> tir/expr_functor.h, tir/stmt_functor.h

* unify vm and interpreter objects

* move closure back vm

* adt/closure back to vm.adt/vm.closure

* closure base

- Fixes issues to enable fp16 vectorizer. Now correct packing and
  unpacking CUDA code will be emitted. Enabled more unit tests.

- Do not emit code to read the first lane from an undef variable

  int _3;
  _3 = _3 & ~(0x000000ff << 0) | ...

  and emit the following code instead:

  _3 = (((0x000000ff & (_1 >> 0))+(0x000000ff & (_2 >> 0))) << 0);

  Note that nvcc 10.2 is forgiving and emits the same code for both cases.
  A warning appears in test_codegen_cuda.py.

Signed-off-by: Wei Pan <weip@nvidia.com>

* Update task_python_vta.sh

* install sbt=1.1.1 with apt-get

* update verilator_opt

* install verilator with major version 4.0

* disable multi-threading for now

* bug fix for correcting uop fetch address in LoadUop module

* bug fix for correcting uop fetch address in LoadUop module

* adjustment to read from dram_offset

* enable USE_THREADS with verilator 4.x

* DEBUG: try avoid core dump with verilator 4.x

* bug fix in LoadUop module

* log mega cycles in tsim

* download cat.png to avoid fetching in each run

* bug fix in LoadUop module

* solve dram_even/sram_even issue

* bug fix

* introduce scalalint in ci

* speedup tsim in ci

* bug fix

* lint scala code before building

* disable multi-threading

* split fsim/tsim script

* update Jenkins settings

* duplicate task_python_vta_fsim.sh as task_python_vta.sh for now

Co-authored-by: Thierry Moreau <tmoreau@octoml.ai>

Move the conversion extensions to the specific class definitions
so that we longer need to include packed_func_ext.

During Unified IR refactor we will change the structure of IRs.
This will cause certain historical modules stored via json no longer
able to be loaded by the current version.

This PR introduces a backward compatible layer to try its best effort
to upgrade json from previous version(this case 0.6) to the current version.
We mainly aim to support update of high-level ir(relay).

* [QNN] Conv2D type checking for kernel per-channel scales.

* Address commments.

* Address comments.

* - Adding safety checks for downcasts.

Co-authored-by: shoubhik <shoubhikbhatti@gmail.com>

* [VTA] Update Jenkinsfile for VTA test with TSIM

* duplicate task_python_vta.sh multiple copies for now

- Remove operator bool from base object ref macro
  - Raitionale: operator bool can be dangerous for sub-classes
    that also overloads other operators(e.g. ==).
  - If bool is still needed, use explicit operator bool.
- Use absolute include when necessary
- Move type related util to data_type
- Isolate stackvm code from compiler

* [Docs] Convert Layout pass.

* Address comments. Section 3 massaging.

* Address comments.

* [REFACTOR] introduce top - Tensor Operation DSL.

Historically we put Tensor, Schedule and compute under the root tvm namespace.
This is no longer a good idea as the project's scope grows larger
than the tensor operation DSL.

This PR introduces top -- a namespace for tensor operational
DSL concepts such as schedule, tensor, compute.
We moved the related files to the new top subfolder.

* Move relevant files into include/tvm/top and src/top

* BYOC tutorial: codegen C

* Address comments

* Address comments

* Add build option

* Address comments

* Use TVM_DLL_EXPORT_TYPED_FUNC

Spread the arithmetic.h into several components and move
into arith subfolder.

The arith namespace will be used for arithmetic expression
pattern detections and simplifications.

* [Relay][Frontend][TFLite] Add parser support for squared difference

* fix some error

* fix exp_type

* add comment

* [arith] add ShapeVar representing non-neg valued variable in a tensor shape

* bounder remover; deal with div in int_set differently

* fix bounder_remover

* migrate unittest to use shape_var

* use tvm.shape_var in integration & relay tests

* add test case; fix Var register

* fix lint

* fix lint again

* add default ShapeVar visitor in Relay

* fix override

* fix ShapeVar visit bug

* revert IntervalSet for shape_var

* remove bound_remover

* remove is_var; use constructor for shapevar/var instead

* ShapeVar -> SizeVar; add constructor comments

* shape_var -> size_var in doc

* tindex -> size

As part of Unified IR infra.
Introduce target folder to store all the compilation target related information.

This PR introduces more clear naming prefix for C API type codes
to avoid conflict with other packages.

We also removed TVMArray and TVMType to directly use DLTensor and DLDataType.

* [REFACTOR] Move support related code to include/tvm/support

- tvm/logging.h -> tvm/support/logging.h
- remove tvm/base.h, move with into tvm/support/with.h

* src/common -> src/support

This PR moves attrs.h into the ir folder as it
can serve as a common infra for building ir dats structures.

We also moved common container(FloatImm) into ir/expr.h

* [Relay][Frontend][TFLite] Add constant input support for elemwise ops

* modify in tflite.py

This reverts commit dcf7fbf1.

* [REFACTOR][IR] Unify IntImm and UIntImm

This PR unifies UIntImm and IntImm to simplify the codebase.
Unsigned integer constants will also be stored as IntImm.

For uint constant that does not fit into int64(rare case), we introduced
an intrinsic tvm_big_uint_imm to construct such intgers by its
lower and higher 32bits.

* [REFACTOR][IR] Remove UIntImm to use IntImm

* rename big->large

- Use consistent constructor style to construct objects.
- Move env_func to ir as it is mainly used to construct IRs.
- Make docs consistent.

* [relay] Relay annotation and partitioning for codegen

* Add fusion unit test

* fix comments

* Update include/tvm/relay/attrs/annotation.h

Co-Authored-By: 雾雨魔理沙 <lolisa@marisa.moe>

* rebase

* remove annotation helper

* rebase again

Co-authored-by: Cody Yu <comaniac0422@gmail.com>
Co-authored-by: 雾雨魔理沙 <lolisa@marisa.moe>

Move the relay's pass Infra to ir.
Keep FunctionPass in relay as it is local to the dialect.