- 31 Mar, 2020 1 commit
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* refactor * path udpate
Thierry Moreau committed
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- 30 Mar, 2020 1 commit
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* [CI] Improve VTA build message and scripts. * Use absolute path to set the env var
Tianqi Chen committed
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- 29 Mar, 2020 2 commits
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Tianqi Chen committed
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Thierry Moreau committed
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- 20 Mar, 2020 1 commit
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* [TOPI][OP] Use Thrust sort for argsort and topk The current GPU sort implementation (odd-even transposition sort) is too slow when the number of elements is large. This PR introduces Thrust implementation of sort which is much faster. Note that this change requires CMake 3.8 or later since we have to use nvcc to compile a thrust code. * cmake: make CUDA optional * allow .cu file to be into the repository * pylint fix and cleanup * require cmake 3.8 only when thrust is enabled * fix nvcc compiler error when passing -pthread * add missing include * add USE_THRUST option in config.cmake * retrigger CI * retrigger CI
MORITA Kazutaka committed
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- 12 Mar, 2020 1 commit
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Thierry Moreau committed
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- 10 Mar, 2020 1 commit
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* Add Nick's changes's squashed * Fix frontend compilation * Re-enable Rust CI * Add changes with conflicted badly * Restructure import_module! macro in order to avoid unstable features * Kill old unstable feature enablement * Refactor common to use new APIs * Move the code to stable * Fix warning Co-authored-by: Nick Hynes <nhynes@oasislabs.com>
Jared Roesch committed
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- 09 Mar, 2020 1 commit
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* [VTA][de10nano] Enable user defined target frequency. Issue: The VTA target frequency on the DE10-Nano is hardcoded to 50MHz unnecessarily limiting performance. Solution: Add a PLL to the FPGA sub-system along with support for the selection of a user specified frequency at build time. The board successfully builds and runs at 100MHz. * Added a PLL in the soc_system.tcl platform designer generator script. * Modified the Makefile to automatically set the target frequency from that specified in the pkg_config.py file. * Modified the Makefile to generate a bitstream with an RBF format that enables programming of the FPGA directly from the on-board processor. Specifically, the RBF is generated in FastParallel32 mode with compression, which corresponds to the default MSEL switch setting on the board, i.e. 01010. * Added a false path override to file set_clocks.sdc to turn off unconstrained path warnings on the VTA pulse LED. * [VTA][TSIM] Add more debug and tracing options. * Modified Makefile to change default config to DafaultDe10Config. * Added option in Makefile to produce more detailed tracing for extra observability in debugging complex scenarios. * Added option in Makefile to produce traces in FST format which are 2 orders of magnitude smaller, although much slower to generate. * Added option in Makefile to build the simulator with GCC address sanitizer. * Modified Makefile to not lint the scala code by default avoiding unintended wrong indentation. Linting should be better performed manually on a per-need basis. * [VTA][de10nano] Enable remote programming of FPGA. Issue: The Cyclone V FPGA on board of the DE10-Nano can only be programmed using the JTAG port, which is a limiting option for users. Solution: Add support for the remote programming of the FPGA implementing the FPGA programming manager protocol published in the Cyclone V user manual. * Added file de10nano_mgr.h implementing an FPGA manager class that supports handling of control and status registers as well as a push-button option to program the FPGA. The class can be easily extended to include more registers if needed. * Used an instance of the FPGA manager to implement function VTAProgram also warning users when incompatible bitstream files are used. * Registered VTAProgram as a global function and modified the program_bitstream python class to use it. * [VTA][de10nano] Enhance de10nano runtime support. Issue: The de10nano target has incomplete, non-working support for runtime reconfiguration, bitstream programming, and examples of usage. Solution: Complete runtime support for the de10nano target. * Modified VTA.cmake to comment out a default override for VTA_MAX_XFER to 21 bit wide. * Modified VTA.cmake to add needed de10nano include dirs. * Modified relevant files to support de10nano same way as other targets for VTA runtime reconfiguration and FPGA programming. * Added test_program_rpc.py example as a runtime FPGA programming example. Note that unlike the pynq target no bitstream is either downloaded or programmed when the bitstream argument is set to None. * Cosmetic changes to vta config files. * [VTA][Chisel] LoadUop FSM bug fix. Issue: The LoadUop FSM incorrectly advances the address of the next uop to read from DRAM when the DRAM data valid bit is deasserted and asserted at the end of a read. This is caused by a mismatch in the logic of the state and output portions of the FSM. This is one of two issues that was gating the correct operation of VTA on the DE10-Nano target. Solution: Modify the logic of the output section of the FSM to include a check on the DRAM read valid bit or fold the output assignemnt into the state section. * Folded the assignemnt of the next uop address in the state section of the FSM. * [VTA][Chisel] Dynamically adjust DMA tranfer size. Issue: In the DE10-Nano target and possibly in others, DMA transfers that cross the boundaries of memory pages result in incorrect reads and writes from and to DRAM. When this happens depending on different input values, VTA loads and stores exhibit incorrect results for DMA pulses at the end of a transfer. This is one of two issues that were gating the DE10-Nano target from functioning correctly, but may affect other Chisel based targets. Solution: Add support for dynamically adjustble DMA transfer sizes in load and store operations. For a more elegant and modular implementation the feature can be enabled at compile time with a static constant that can be passed as a configuration option. * Modified the load and store finite state machines to dynamically adjust the size of initial and stride DMA transfers. The feature is enabled by default by virtue of the static constant ADAPTIVE_DMA_XFER_ENABLE. * [VTA][Chisel] Improve FSIM/TSIM/FPGA xref debug. Issue: Cross reference between FSIM, TSIM, and Chisel based FPGA traces is an invaluable instrument that enables fast analysis on FSIM, and analysis/debug on TSIM and FPGA, especially for complex flows like conv2d or full inferences. Currently this cannot be done easily since a suitable reference is missing. The clock cycle event counter cannot be used since it is undefined in FSIM and not reliable between TSIM and FPGA because of different latencies. Solution: Introduce a new event counter that preserves a program order across FSIM, TSIM, FPGA. We propose adding the accumulator write event counter in the Chisel EventCounter class and a simple instrumentation in the FSIM runtime code. Note that this technique enabled finding the Chisel issues reportes in the PR, which would have been otherwise far more difficult. * Added the acc_wr_count event counter and changed interfaces accordingly. * [VTA][de10nano] Comply with linting rules. * [VTA] Appease make lint. * [VTA] Disable pylint import not top level error. * [VTA][Chisel,de10nano] Linting changes. * Use CamelCase class names. * Use C++ style C include header files. * Add comments to Chisel makefile. * [VTA][de10nano] * Reorder C and C++ includes in de10nano_mgr.h. * Restore lint as default target in Chisel Makefile. * [VTA][de10nano] Do not use f string in pkg_config.py. * [VTA][de10nano] Remove overlooked f strings in pkg_config.py. * [VTA][de10nano] Fixed typo. * [VTA][TSIM] Check if gcc has align-new. * [VTA][Chisel] Make adaptive DMA transfer default. * [VTA][RPC] Renamed VTA_PYNQ_RPC_* to VTA_RPC_*. Issue: With more FPGA targets coming online the initial method of using individual environment variables to specify target IP and port does not scale well. Solution: Use a single VTA_RPC_HOST, VTA_RPC_PORT pair to be changed every time a different target is used. For instance in a script used to benchmark all targets. * Replaced every instance of VTA_PYNQ_RPC_HOST and VTA_PYNQ_RPC_PORT with VTA_RPC_HOST and VTA_RPC_PORT, respectively. * [VTA][Chisel] Comply with new linter.
Pasquale Cocchini committed
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- 05 Feb, 2020 1 commit
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Haichen Shen committed
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- 27 Jan, 2020 1 commit
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* Explicitly link to cublasLt * Only link cublasLt if it's found Co-authored-by: Jon Soifer <jonso@microsoft.com>
Jon Soifer committed
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- 19 Jan, 2020 1 commit
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This PR moves the codegen related code into the target folder, as they are target specific functionalities. We also adopt the term "compiler driver" in common compiler infra such as rust, GHC and clang. As a result, build_module is moved into the driver folder.
Tianqi Chen committed
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- 16 Jan, 2020 1 commit
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Thierry Moreau committed
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- 18 Dec, 2019 1 commit
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Zhi committed
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- 04 Dec, 2019 1 commit
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ziheng committed
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- 15 Nov, 2019 1 commit
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* [Contrib] Add MKL DNN * update * update
Haichen Shen committed
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- 31 Oct, 2019 1 commit
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* [CI] Update the ci-gpu to use cuda10 * [CI] Enforce tensorcore gpu for unittest
Tianqi Chen committed
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- 27 Oct, 2019 1 commit
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Tianqi Chen committed
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- 24 Oct, 2019 1 commit
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* Support setting path to ANTLR jar * Update comment
Jon Soifer committed
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- 20 Oct, 2019 1 commit
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Haichen Shen committed
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- 08 Oct, 2019 1 commit
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Issue: git clone latest TVM/VTA and run VTA on xilinx FPGA board, application crashed due to the "call stack overflow" which caused by a infinite recursive function call. this issue ever happen before and get addressed by PR 3843. Analysis: seems like de10-nano driver PR used old code base then the logic change of 3843 get eliminated. Solution: add the logic back.
Hua Jiang committed
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- 13 Sep, 2019 1 commit
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Andrew Tulloch committed
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- 12 Sep, 2019 1 commit
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This is an alternative implementation of a subset of the TVM runtime API (and graph runtime) that focuses entirely on reducing code size, at the expense of functionality (no tvm.extern(..) calls via PackedFunc, CPU only, etc). It might be worth incrementally expanding the surface area if there's interest. The motivation for this work was seeing what the minimal useful subset of the TVM runtime is. This is relevant for e.g. super code-size constrained applications in e.g. embedded/mobile. The current runtime is more like O(100KiB) or so, so this might be compelling for some users. The smaller surface area for auditing might make this relevant for https://github.com/dmlc/tvm/issues/3159, or the usecases I was thinking about in https://github.com/dmlc/tvm/issues/2523#issuecomment-459165815 re: the Rust runtime. The symbols in the tvm::minimalruntime space (i.e. excluding std:: and picojson::) are about 5KiB, so I think there's a bunch of room here (i.e. we could replace picojson:: with [`jsmn`](https://zserge.com/jsmn.html) or something, and we could replace more of the `std::unordered_map` usage, etc with custom primitives as well (similar to the `DynArray`).
Andrew Tulloch committed
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- 07 Sep, 2019 2 commits
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* fix cmake for mac os * rename
Haichen Shen committed -
* [VTA] Support TLPP in function simulator. Issue: currently vta function simulator just doing serialized instruction execution, the dependency logic of runtime ISA which use for task level pipe line parallelism can not get verified by function simulator. Solution: make the simulator driver to be multiple thread and support TLPP. Benefit: TLPP support VTA function simulator would make VTA logic testing/debug /change more easy. replace boost lockfree queue add configure control for simulator tlpp enable or disable. change code tyle into google style. Wrap queue read/write and sync logic to make function call more simple. Add some comments. Remove MT logic, change into Single thread mode. address review comments. code style change to match google code style and add comments. add cmake macro to enable/disable simulator tlpp logic. submodule update. correct file name mentioned in comments. * remove USE_VTA_FSIM_TLPP.
Hua Jiang committed
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- 06 Sep, 2019 1 commit
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Installed through pypi
Jason Knight committed
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- 05 Sep, 2019 1 commit
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* rework; * `de10-nano` -> `de10nano`; * fix compilation error; * bug fix; * Update install.md * Update install.md * Update install.md * update with current runtime; * add debug messages; * bug fix in cma kernel module;
Liangfu Chen committed
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- 02 Sep, 2019 1 commit
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Luis Vega committed
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- 29 Aug, 2019 2 commits
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Issue when try vta on fpga board, would see a Infinite recursive device_api.ext_dev issue that cause stack overflow and vta failed. Analysis: device_api.ext_dev function in rpc_server.py is use to load vta library, once vta library get load, device_api.ext_dev would get replaced with vta function by vta library, vta device_api.cc did such work, but because a logic issue in VTA.cmake, the said file not get compiled, then vta would keep failing on rpc_server.py. Solution: fix the logic issue in VTA.cmake.
Hua Jiang committed -
Jon Soifer committed
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- 26 Aug, 2019 1 commit
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* initial virtual memory; * initial integration; * include the header file in cmake; * implement allocation with virtual to logical address mapping; * virtual memory for tsim_driver; * implement the missing memory release function; * readability improvement; * readability improvement; * address review comments; * improved robustness in virtual memory allocation; * remove VTA_TSIM_USE_VIRTUAL_MEMORY macro and use virtual memory for tsim by default; * link tvm against vta library; * merge with master * build virtual memory system without linking tvm against vta; * minor change; * reuse VTA_PAGE_BYTES; * using DRAM class from sim_driver as VirtualMemoryManager; * satisfy linter; * add comments in code; * undo changes to Makefile * undo changes to Makefile * retrigger ci; * retrigger ci; * directly call into VirtualMemoryManager::Global()
Liangfu Chen committed
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- 13 Aug, 2019 1 commit
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* building TSIM specific library along with fast simulator to quickly switch between dlls * cmake controlled TSIM libraries * always build tsim driver in either simulation modes * build DLLs based on CMAKE flags * updating the jenkinsfile * small restructuring * reducing the cmake flags * update instructions * reverting to 3 flags * update Jenkinsfile * adding new line * enabling TSIM unit and integration tests * fix description * temporarily disabling task_python_vta tests in CPU Build stage * move CPU tests in unit test stage * stage reorg * better make * disabling TSIM tests for now * reverting some restructuring * fix
Thierry Moreau committed
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- 29 Jul, 2019 2 commits
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Luis Vega committed
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* hardware refactor for increased FPGA coverage, small optimizations * fix header * cleaning up parameters that won't be needed for now * streamlining makefile, and simplifying tcl scripts * moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight * refactoring tcl script to avoid global variables * deriving AXI signals in pkg_config.py * unifying address map definition for hardware and software drivers * single channel design for ultra96 to simplify build * enable alu by default, no mul opcode for now * hardware fix * new bitstream; vta version * avoid error when env variable is not set * ultra96 cleanup * further cleaning up tcl script for bitstream generation * preliminary rpc server support on ultra96 * rpc server tracker scripts * ultra96 ldflag * ultra96 support * ultra96 support * cleanup line * cmake support for ultra96 * simplify memory instantiation * cleaning up IP parameter initialization * fix queue instantiation * 2019.1 transition * fix macro def * removing bus width from config * cleanup * fix * turning off testing for now * cleanup ultra96 ps insantiation * minor refactor * adding comments * upgrading to tophub v0.6 * model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling * revert change due to bug * rename driver files to be for zynq-type devices * streamlining address mapping * unifying register map offset values between driver and hardware generator * rely on cma library for cache flush/invalidation * coherence management * not make buffer packing depend on data types that can be wider than 64bits * refactor config derivation to minimize free parameters * fix environment/pkg config interaction * adding cfg dump property to pkgconfig: * fix rpc reconfig * fix spacing * cleanup * fix spacing * long line fix * fix spacing and lint * fix line length * cmake fix * environment fix * renaming after pynq since the driver stack relies on the pynq library - see pynq.io * update doc * adding parameterization to name * space * removing reg width * vta RPC * update doc on how to edit vta_config.json * fix path * fix path
Thierry Moreau committed
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- 25 Jul, 2019 1 commit
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* uTVM interfaces (#14) * some minor interface changes * implemented HostLowLevelDevice * added MicroDeviceAPI * implemented micro_common and added Python interfaces * current status, semi implemented micro session * added micro_common implementation and python interfaces (#18) * added micro_common implementation and python interfaces (#18) * current status, semi implemented * host test working * updated interfaces for MicroSession arguments allocation * make somewhat lint compatible * fix based on comments * added rounding macro * fix minor bug * improvements based on comments * Clean up `binutil.py` and make Python-3-compatible * Change argument allocation design * Address feedback and lint errors * Improve binutil tests * Simplify allocator (per @tqchen's suggestions) * Doc/style fixes * farts * mcgee * rodata section werks (and so does `test_runtime_micro_workspace.py`) * simple graph runtime werk * TEMP * ResNet works, yo * First round of cleanup * More cleanup * runs a dyson over the code * Another pass * Fix `make lint` issues * ready to pr... probably * final * Undo change * Fix rebase resolution * Minor fixes * Undo changes to C codegen tests * Add `obj_path` in `create_micro_lib` * TEMP * Address feedback * Add missing TODO * Partially address feedback * Fix headers * Switch to enum class for `SectionKind` * Add missing ASF header * Fix lint * Fix lint again * Fix lint * Kill lint warnings * Address feedback * Change Python interface to MicroTVM All interaction with the device is now through `Session` objects, which are used through Python's `with` blocks. * Reorder LowLevelDevice interface * Store shared ptr to session in all alloced objects * Move helper functions out of `tvm.micro` * Switch static char arr to vector * Improve general infra and code quality Does not yet address all of tqchen's feedback * Forgot a rename * Fix lint * Add ASF header * Fix lint * Partially address MarisaKirisame's feedback * Lint * Expose `MicroSession` as a node to Python * Revert to using `Session` constructor * Fix compiler error * (Maybe) fix CI error * Debugging * Remove * Quell lint * Switch to stack-based session contexts * Make uTVM less intrusive to host codegen And use SSA for operands of generated ternary operators * Inline UTVMArgs into UTVMTask struct * Remove `HostLowLevelDevice` header * Remove `BaseAddr` class * Address feedback * Add "utvm" prefix to global vars in runtime * Fix lint * Fix CI * Fix `test_binutil.py` * Fix submodules * Remove ResNet tests * Make `test_binutil.py` work with nose * Fix CI * I swear this actually fixes the binutil tests * lint * lint * Add fcompile-compatible cross-compile func * Add docs for uTVM runtime files * Move pointer patching into `MicroSession` * Fix lint * First attempt at unifying cross-compile APIs * Fix lint * Rename `cross_compile` back to `cc` * Address feedback * Remove commented code * Lint * Figure out failing function * Remove debugging code * Change "micro_dev" target to "micro" * Add checks in tests for whether uTVM is enabled * Add TODO for 32-bit support * Rename more "micro_dev" to "micro" * Undo rename We already have `tvm.micro` as a namespace. Can't have it as a method as well. * Fix failing CI Thanks to @tqchen for finding this bug. Emitting ternary operators for `min` and `max` causes concurrency bugs in CUDA, so we're moving the ternary op emissions from `CodeGenC` to `CodeGenCHost`. * Address feedback * Fix lint
Logan Weber committed
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- 09 Jul, 2019 1 commit
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* init fix rebase lint fix cmake try again fix ci * add gitignore * fix format * do not include .interp and .tokens
雾雨魔理沙 committed
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- 28 Jun, 2019 1 commit
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* simplify build script, remove python 2 support * remove py2 file * update py3
雾雨魔理沙 committed
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- 05 Jun, 2019 1 commit
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Luis Vega committed
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- 01 Jun, 2019 1 commit
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* [Bugfix][VTA] PkgConfig cause crash in PYNQ board due to link library not exist. Symptom: When run vta_get_started.py with pynq board, host crash and complain "cannot find -lsds_lib" and "cannot find -l:libdma.so" Reproduce: At pynq board, delete the ./build/vta_config.json, then run rpc server. In host machine run vta_get_started.py, issue would reproduce. Analysis: This issue caused by 'PkgConfig' function still using pynq2.1 library which not exist in pynq2.4 anymore, when a "reconfig_runtime" logic of rpc_server.py get triggered , the compile would failed due to link library not exist. Solution: change the link library to libcma.so. * [Document Change][VTA] Change pynq version from 2.3 into 2.4. Issue: pynq 2.3 image not available anymore from pynq download page and pynq 2.4 is the current latest image which available in the said website, after verification, currently VTA work good with pynq 2.4 image, hence update related document from pynq 2.3 to 2.4.
Hua committed
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- 21 May, 2019 1 commit
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hlu1 committed
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- 08 May, 2019 1 commit
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* merge files * move verilator to the right place * change name to tsim * add default rule to be build and run * add README for tsim * Update README.md * add some structural feedback * change name of VTASim to VTADPISim * more renaming * update comment * add license * fix indentation * add switch for vta-tsim * add more licenses * update readme * address some of the new feedback * add some feedback from cpplint * add one more whitespace * pass pointer so linter is happy * pass pointer so linter is happy * README moved to vta documentation * create types for dpi functions, so they can be handle easily * fix pointer style * add feedback from docs * parametrize width data and pointers * fix comments * fix comment * add comment to class * add missing parameters * move README back to tsim example * add feedback * add more comments and remove un-necessary argument in finish * update comments * fix cpplint * fix doc
Luis Vega committed
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