* [DOC] Add intro to 'comm_reducer' in tutorial; fix doc

* Fix

* Fix

* [PYTHON/FFI] Enable Cython FFI

* fix cython

* [LANG] CommReducer

* Reorganize c_api

* Remove InitValue and Combine; refactor Functor

* Make CommReducer an Expr

* Make comm_reducer type independent

* Make CommReducerNode a Node

* Small fix

* Refine

* Refine front api; add integration testcases for min/max

* Fix python

* Refine

* Fix lint and add example

* [PASS] StorageRewrite, reuse memory pass as in NNVM.

* fix issue

* [LANG/CODEGEN] Intrinsics and Extern Math

* fix lint

* [DOC] Scan tutorial

* Fix according to ziheng's comment

* [PERF] Add gemm

* [DOC] Reduction tutorial

* [DOC] Add schedule_computaion

* Finetune the doc

* Finetune the doc

* Finetune the doc

* Set max_unroll_step=0 by default

* [DOC] API doc organization.

* remove breathe for now

* Add setup.py, fix comments

* Update installation document

* [DOC] Initial doc system

* Migrate API

* Update docs

* [PERF] Persitent kernel

* fix doc

* [PASS] Support for partition loops with thread_axis

* Add check for AttrStmt.attr_key

* [SCHEDULE] Add group, refactor thread bind api.

* fix doc

* fix g++-4.8

* More testscase

* Remove graph context from fix pt analysis

* [LANG/GPU] Cross Thread Reduction.

* Fix doxygen error

* Upgrade verilog testcase to new one

* adding tvm_buffer and fifo testbench

* minor edits

* line buffer test bench

* adding double buffer tests for the tvm_buffer

* making variable consistent with  python style

* [CODEGEN] Refactor common codegen, Verilog Codegen

* fix make

* fix mk

* update enable signal

* change function name to at neg edge

* Move test to correct place

* [VERILOG] VPI Mem Interface/ VPI MMap

* fix test issues

* [RUNTIME] Refactor runtime to be DLPack compatible. Enable plugin of new runtime.

* fix mac compile

* ok

* [VERILOG] Basic Verilog Testflow

* fix build

* fix the comment

* fix lint in verilog

* [OP/LANG] Support Extern Call, more regression tests

* [TEST] Include pylintrc