- 18 Apr, 2017 3 commits
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* [DOC] Add schedule_computaion * Finetune the doc * Finetune the doc * Finetune the doc * Set max_unroll_step=0 by default
ziheng committed -
Tianqi Chen committed
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Tianqi Chen committed
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- 17 Apr, 2017 2 commits
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Tianqi Chen committed
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Tianqi Chen committed
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- 16 Apr, 2017 1 commit
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* [DOC] API doc organization. * remove breathe for now
Tianqi Chen committed
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- 15 Apr, 2017 3 commits
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* Add setup.py, fix comments * Update installation document
ziheng committed -
* [DOC] Initial doc system * Migrate API * Update docs
Tianqi Chen committed -
* [PERF] Persitent kernel * fix doc
Tianqi Chen committed
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- 13 Apr, 2017 1 commit
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Tianqi Chen committed
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- 11 Apr, 2017 1 commit
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Tianqi Chen committed
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- 10 Apr, 2017 2 commits
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Tianqi Chen committed
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* [PASS] Support for partition loops with thread_axis * Add check for AttrStmt.attr_key
ziheng committed
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- 09 Apr, 2017 2 commits
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Tianqi Chen committed
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* [SCHEDULE] Add group, refactor thread bind api. * fix doc * fix g++-4.8 * More testscase * Remove graph context from fix pt analysis
Tianqi Chen committed
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- 02 Apr, 2017 1 commit
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Tianqi Chen committed
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- 01 Apr, 2017 1 commit
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* [LANG/GPU] Cross Thread Reduction. * Fix doxygen error * Upgrade verilog testcase to new one
Tianqi Chen committed
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- 29 Mar, 2017 1 commit
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Tianqi Chen committed
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- 27 Mar, 2017 1 commit
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* adding tvm_buffer and fifo testbench * minor edits * line buffer test bench * adding double buffer tests for the tvm_buffer * making variable consistent with python style
Thierry Moreau committed
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- 26 Mar, 2017 3 commits
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Tianqi Chen committed
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Tianqi Chen committed
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* [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place
Tianqi Chen committed
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- 17 Mar, 2017 1 commit
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* [VERILOG] VPI Mem Interface/ VPI MMap * fix test issues
Tianqi Chen committed
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- 14 Mar, 2017 2 commits
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* [RUNTIME] Refactor runtime to be DLPack compatible. Enable plugin of new runtime. * fix mac compile * ok
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* [VERILOG] Basic Verilog Testflow * fix build * fix the comment * fix lint in verilog
Tianqi Chen committed
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- 12 Mar, 2017 2 commits
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* [OP/LANG] Support Extern Call, more regression tests * [TEST] Include pylintrc
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Tianqi Chen committed
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- 07 Mar, 2017 1 commit
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Tianqi Chen committed
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- 05 Mar, 2017 1 commit
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* [IterVar/REFACTOR] Add types to IterVar * [ARITH/REFACTOR] Move IntSet to include * [REFACTOR/OP] Move Op detail to seperate folder. * fix test
Tianqi Chen committed
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- 04 Mar, 2017 1 commit
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* loop_partition draft * divide loop variable into constant domain and variable domain & consider multiple partitions * process doubt interval * fix and refactor, add relax_map arg in BoundDeduce * fix testcase and comment * rebase to zero, convert to SSA * change the logic of generating loop code & fix issues * add a testcase for relax map in deducebound && fix issues * clean code * const auto& * add test_multi_if
Ziheng Jiang committed
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- 03 Mar, 2017 1 commit
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Tianqi Chen committed
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- 02 Mar, 2017 1 commit
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Tianqi Chen committed
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- 01 Mar, 2017 2 commits
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Tianqi Chen committed
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* [ARITH/VISITOR] Modular Analysis, ExprFunctor, StmtFunctor * retrigger * [IRFunctor] Migrated CodegenC * [IRFUNCTOR] Migrate CodeGenLLVM * [IRFunctor] Migrate canonical * [IRFunctor] Migrate vectorize * [IRFunctor] migrate CodeGenStackVM
Tianqi Chen committed
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- 27 Feb, 2017 1 commit
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Tianqi Chen committed
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- 26 Feb, 2017 3 commits
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Tianqi Chen committed
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Tianqi Chen committed
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Tianqi Chen committed
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- 24 Feb, 2017 1 commit
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Tianqi Chen committed
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- 22 Feb, 2017 1 commit
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* [LLVM] Initial support for codegen LLVM. * Fix the naming issue of codegen
Tianqi Chen committed
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